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* [PATCH V5 0/4] additional features to Tegra SPI
@ 2019-05-14  5:03 Sowjanya Komatineni
  2019-05-14  5:03 ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
                   ` (3 more replies)
  0 siblings, 4 replies; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-14  5:03 UTC (permalink / raw)
  To: thierry.reding, jonathanh, ldewangan, broonie
  Cc: linux-tegra, linux-kernel, linux-spi, Sowjanya Komatineni

[V5] : This patch series version includes
	- Updated GPIO based chip select control using GPIO descriptor.
	- HW based chip select implementation is same as V3 but V5
	  has this patch updated to be on top of above changes.
	- HW CS timing implementation is same as V3 but V5
	  has this patch updated to be on top of above changes.
	- support for TX and RX trimmers implementation is same as V3
	  but V5 has this patch updated to be on top of above changes
	  and updated commit description.

[V4] : This version went out accidentally. Please discard.

[V3] : This patch series version includes
	- only patches that are not applied from V2.
	- splitted expanding mode and adding LSByte First support
	  in separate patches and removed DT property for selecting
	  LSByte First.
	- Updated GPIO based chip select control to use spi_set_cs
	  from SPI core.
	- HW based chip select implementation is same as V2 but V3
	  has this patch updated to be on top of above changes.
	- HW CS timing implementation is same as V2 but V3
	  has this patch updated to be on top of above changes.
	- support for TX and RX trimmers implementation is same as V2
	  but V3 has this patch updated to be on top of above changes
	  and updated commit description.

[V2] : This patch series version includes
	- only patches that are not applied from V1.
	- changed order of patches to include all fixes prior to new features
	  support.
	- Removed HW CS timing from DT properties and created set_cs_timing
	  SPI master optional method for SPI controllers to implement and
	  created API spi_cs_timing for SPI client drivers to request CS
	  setup, hold and inactive delay timing configuration.
	- Fixed HW based CS decision to be based on single transfer and
	  cs_change. Remove selection of HW based CS through DT.


Sowjanya Komatineni (4):
  spi: tegra114: add support for gpio based CS
  spi: tegra114: add support for hw based cs
  spi: tegra114: add support for HW CS timing
  spi: tegra114: add support for TX and RX trimmers

 drivers/spi/spi-tegra114.c | 167 ++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 151 insertions(+), 16 deletions(-)

-- 
2.7.4


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
  2019-05-14  5:03 [PATCH V5 0/4] additional features to Tegra SPI Sowjanya Komatineni
@ 2019-05-14  5:03 ` Sowjanya Komatineni
  2019-05-14  9:33   ` Jon Hunter
  2019-05-15 11:18   ` Applied "spi: tegra114: add support for gpio based CS" to the spi tree Mark Brown
  2019-05-14  5:03 ` [PATCH V5 2/4] spi: tegra114: add support for hw based cs Sowjanya Komatineni
                   ` (2 subsequent siblings)
  3 siblings, 2 replies; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-14  5:03 UTC (permalink / raw)
  To: thierry.reding, jonathanh, ldewangan, broonie
  Cc: linux-tegra, linux-kernel, linux-spi, Sowjanya Komatineni

This patch adds support for GPIO based CS control through SPI core
function spi_set_cs.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index b1f31bb16659..f47417dd9edb 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -776,6 +776,10 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 		} else
 			tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 
+		/* GPIO based chip select control */
+		if (spi->cs_gpiod)
+			gpiod_set_value(spi->cs_gpiod, 1);
+
 		command1 |= SPI_CS_SW_HW;
 		if (spi->mode & SPI_CS_HIGH)
 			command1 |= SPI_CS_SW_VAL;
@@ -864,6 +868,10 @@ static int tegra_spi_setup(struct spi_device *spi)
 	}
 
 	spin_lock_irqsave(&tspi->lock, flags);
+	/* GPIO based chip select control */
+	if (spi->cs_gpiod)
+		gpiod_set_value(spi->cs_gpiod, 0);
+
 	val = tspi->def_command1_reg;
 	if (spi->mode & SPI_CS_HIGH)
 		val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
@@ -893,6 +901,10 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 	int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
 
+	/* GPIO based chip select control */
+	if (spi->cs_gpiod)
+		gpiod_set_value(spi->cs_gpiod, 0);
+
 	if (cs_val)
 		tspi->command1_reg |= SPI_CS_SW_VAL;
 	else
@@ -1199,6 +1211,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
 		master->max_speed_hz = 25000000; /* 25MHz */
 
 	/* the spi->mode bits understood by this driver: */
+	master->use_gpio_descriptors = true;
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
 			    SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
-- 
2.7.4


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH V5 2/4] spi: tegra114: add support for hw based cs
  2019-05-14  5:03 [PATCH V5 0/4] additional features to Tegra SPI Sowjanya Komatineni
  2019-05-14  5:03 ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
@ 2019-05-14  5:03 ` Sowjanya Komatineni
  2019-05-15 11:18   ` Applied "spi: tegra114: add support for hw based cs" to the spi tree Mark Brown
  2019-05-14  5:03 ` [PATCH V5 3/4] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
  2019-05-14  5:03 ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni
  3 siblings, 1 reply; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-14  5:03 UTC (permalink / raw)
  To: thierry.reding, jonathanh, ldewangan, broonie
  Cc: linux-tegra, linux-kernel, linux-spi, Sowjanya Komatineni

Tegra SPI controller supports both HW and SW based CS control
for SPI transfers.

This patch adds support for HW based CS control where CS is driven
to active state during the transfer and is driven inactive at the
end of the transfer directly by the HW.

This patch enables the use of HW based CS only for single transfers
without cs_change request.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 39 +++++++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index f47417dd9edb..0cb0932d32fd 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -193,6 +193,7 @@ struct tegra_spi_data {
 	unsigned				dma_buf_size;
 	unsigned				max_buf_size;
 	bool					is_curr_dma_xfer;
+	bool					use_hw_based_cs;
 
 	struct completion			rx_dma_complete;
 	struct completion			tx_dma_complete;
@@ -723,7 +724,9 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 }
 
 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
-		struct spi_transfer *t, bool is_first_of_msg)
+					struct spi_transfer *t,
+					bool is_first_of_msg,
+					bool is_single_xfer)
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 	u32 speed = t->speed_hz;
@@ -780,11 +783,17 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 		if (spi->cs_gpiod)
 			gpiod_set_value(spi->cs_gpiod, 1);
 
-		command1 |= SPI_CS_SW_HW;
-		if (spi->mode & SPI_CS_HIGH)
-			command1 |= SPI_CS_SW_VAL;
-		else
-			command1 &= ~SPI_CS_SW_VAL;
+		if (is_single_xfer && !(t->cs_change)) {
+			tspi->use_hw_based_cs = true;
+			command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
+		} else {
+			tspi->use_hw_based_cs = false;
+			command1 |= SPI_CS_SW_HW;
+			if (spi->mode & SPI_CS_HIGH)
+				command1 |= SPI_CS_SW_VAL;
+			else
+				command1 &= ~SPI_CS_SW_VAL;
+		}
 
 		tegra_spi_writel(tspi, 0, SPI_COMMAND2);
 	} else {
@@ -905,11 +914,14 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
 	if (spi->cs_gpiod)
 		gpiod_set_value(spi->cs_gpiod, 0);
 
-	if (cs_val)
-		tspi->command1_reg |= SPI_CS_SW_VAL;
-	else
-		tspi->command1_reg &= ~SPI_CS_SW_VAL;
-	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	if (!tspi->use_hw_based_cs) {
+		if (cs_val)
+			tspi->command1_reg |= SPI_CS_SW_VAL;
+		else
+			tspi->command1_reg &= ~SPI_CS_SW_VAL;
+		tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	}
+
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 }
 
@@ -936,16 +948,19 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
 	struct spi_device *spi = msg->spi;
 	int ret;
 	bool skip = false;
+	int single_xfer;
 
 	msg->status = 0;
 	msg->actual_length = 0;
 
+	single_xfer = list_is_singular(&msg->transfers);
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 		u32 cmd1;
 
 		reinit_completion(&tspi->xfer_completion);
 
-		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
+		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
+						    single_xfer);
 
 		if (!xfer->len) {
 			ret = 0;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH V5 3/4] spi: tegra114: add support for HW CS timing
  2019-05-14  5:03 [PATCH V5 0/4] additional features to Tegra SPI Sowjanya Komatineni
  2019-05-14  5:03 ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
  2019-05-14  5:03 ` [PATCH V5 2/4] spi: tegra114: add support for hw based cs Sowjanya Komatineni
@ 2019-05-14  5:03 ` Sowjanya Komatineni
  2019-05-15 11:18   ` Applied "spi: tegra114: add support for HW CS timing" to the spi tree Mark Brown
  2019-05-14  5:03 ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni
  3 siblings, 1 reply; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-14  5:03 UTC (permalink / raw)
  To: thierry.reding, jonathanh, ldewangan, broonie
  Cc: linux-tegra, linux-kernel, linux-spi, Sowjanya Komatineni

This patch implements set_cs_timing SPI controller method to allow
SPI client driver to configure device specific SPI CS timings.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 48 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 0cb0932d32fd..e59ff7c1cee6 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -95,8 +95,10 @@
 		(reg = (((val) & 0x1) << ((cs) * 8 + 5)) |	\
 			((reg) & ~(1 << ((cs) * 8 + 5))))
 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)		\
-		(reg = (((val) & 0xF) << ((cs) * 8)) |		\
-			((reg) & ~(0xF << ((cs) * 8))))
+		(reg = (((val) & 0x1F) << ((cs) * 8)) |		\
+			((reg) & ~(0x1F << ((cs) * 8))))
+#define MAX_SETUP_HOLD_CYCLES			16
+#define MAX_INACTIVE_CYCLES			32
 
 #define SPI_TRANS_STATUS			0x010
 #define SPI_BLK_CNT(val)			(((val) >> 0) & 0xFFFF)
@@ -206,6 +208,8 @@ struct tegra_spi_data {
 	u32					command1_reg;
 	u32					dma_control_reg;
 	u32					def_command1_reg;
+	u32					spi_cs_timing1;
+	u32					spi_cs_timing2;
 
 	struct completion			xfer_completion;
 	struct spi_transfer			*curr_xfer;
@@ -723,6 +727,43 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 	dma_release_channel(dma_chan);
 }
 
+static void tegra_spi_set_hw_cs_timing(struct spi_device *spi, u8 setup_dly,
+				       u8 hold_dly, u8 inactive_dly)
+{
+	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
+	u32 setup_hold;
+	u32 spi_cs_timing;
+	u32 inactive_cycles;
+	u8 cs_state;
+
+	setup_dly = min_t(u8, setup_dly, MAX_SETUP_HOLD_CYCLES);
+	hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES);
+	if (setup_dly && hold_dly) {
+		setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
+		spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
+						  spi->chip_select,
+						  setup_hold);
+		if (tspi->spi_cs_timing1 != spi_cs_timing) {
+			tspi->spi_cs_timing1 = spi_cs_timing;
+			tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
+		}
+	}
+
+	inactive_cycles = min_t(u8, inactive_dly, MAX_INACTIVE_CYCLES);
+	if (inactive_cycles)
+		inactive_cycles--;
+	cs_state = inactive_cycles ? 0 : 1;
+	spi_cs_timing = tspi->spi_cs_timing2;
+	SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
+					  cs_state);
+	SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
+				       inactive_cycles);
+	if (tspi->spi_cs_timing2 != spi_cs_timing) {
+		tspi->spi_cs_timing2 = spi_cs_timing;
+		tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
+	}
+}
+
 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 					struct spi_transfer *t,
 					bool is_first_of_msg,
@@ -1232,6 +1273,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 	master->setup = tegra_spi_setup;
 	master->transfer_one_message = tegra_spi_transfer_one_message;
+	master->set_cs_timing = tegra_spi_set_hw_cs_timing;
 	master->num_chipselect = MAX_CHIP_SELECT;
 	master->auto_runtime_pm = true;
 	bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
@@ -1307,6 +1349,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	reset_control_deassert(tspi->rst);
 	tspi->def_command1_reg  = SPI_M_S;
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
+	tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
+	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
 	pm_runtime_put(&pdev->dev);
 	ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
 				   tegra_spi_isr_thread, IRQF_ONESHOT,
-- 
2.7.4


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers
  2019-05-14  5:03 [PATCH V5 0/4] additional features to Tegra SPI Sowjanya Komatineni
                   ` (2 preceding siblings ...)
  2019-05-14  5:03 ` [PATCH V5 3/4] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
@ 2019-05-14  5:03 ` Sowjanya Komatineni
  2019-05-15 11:18   ` Applied "spi: tegra114: add support for TX and RX trimmers" to the spi tree Mark Brown
  2019-05-23  1:02   ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Nathan Chancellor
  3 siblings, 2 replies; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-14  5:03 UTC (permalink / raw)
  To: thierry.reding, jonathanh, ldewangan, broonie
  Cc: linux-tegra, linux-kernel, linux-spi, Sowjanya Komatineni

Tegra SPI master controller has programmable trimmers to adjust the
data with respect to the clock.

These trimmers are programmed in TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY
fields of COMMAND2 register.

SPI TX trimmer is to adjust the outgoing data with respect to the
outgoing clock and SPI RX trimmer is to adjust the loopback clock with
respect to the incoming data from the slave device.

These trimmers vary based on trace lengths of the platform design for
each of the slaves on the SPI bus and optimal value programmed is from
the platform validation across PVT.

This patch adds support for configuring TX and RX clock delay trimmers
through the device tree properties.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 67 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 65 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index e59ff7c1cee6..253a7f182fc9 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -169,6 +169,11 @@ struct tegra_spi_soc_data {
 	bool has_intr_mask_reg;
 };
 
+struct tegra_spi_client_data {
+	int tx_clk_tap_delay;
+	int rx_clk_tap_delay;
+};
+
 struct tegra_spi_data {
 	struct device				*dev;
 	struct spi_master			*master;
@@ -208,8 +213,10 @@ struct tegra_spi_data {
 	u32					command1_reg;
 	u32					dma_control_reg;
 	u32					def_command1_reg;
+	u32					def_command2_reg;
 	u32					spi_cs_timing1;
 	u32					spi_cs_timing2;
+	u8					last_used_cs;
 
 	struct completion			xfer_completion;
 	struct spi_transfer			*curr_xfer;
@@ -770,10 +777,12 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 					bool is_single_xfer)
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
+	struct tegra_spi_client_data *cdata = spi->controller_data;
 	u32 speed = t->speed_hz;
 	u8 bits_per_word = t->bits_per_word;
-	u32 command1;
+	u32 command1, command2;
 	int req_mode;
+	u32 tx_tap = 0, rx_tap = 0;
 
 	if (speed != tspi->cur_speed) {
 		clk_set_rate(tspi->clk, speed);
@@ -836,7 +845,18 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 				command1 &= ~SPI_CS_SW_VAL;
 		}
 
-		tegra_spi_writel(tspi, 0, SPI_COMMAND2);
+		if (tspi->last_used_cs != spi->chip_select) {
+			if (cdata && cdata->tx_clk_tap_delay)
+				tx_tap = cdata->tx_clk_tap_delay;
+			if (cdata && cdata->rx_clk_tap_delay)
+				rx_tap = cdata->rx_clk_tap_delay;
+			command2 = SPI_TX_TAP_DELAY(tx_tap) |
+				   SPI_RX_TAP_DELAY(rx_tap);
+			if (command2 != tspi->def_command2_reg)
+				tegra_spi_writel(tspi, command2, SPI_COMMAND2);
+			tspi->last_used_cs = spi->chip_select;
+		}
+
 	} else {
 		command1 = tspi->command1_reg;
 		command1 &= ~SPI_BIT_LENGTH(~0);
@@ -892,9 +912,42 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi,
 	return ret;
 }
 
+static struct tegra_spi_client_data
+	*tegra_spi_parse_cdata_dt(struct spi_device *spi)
+{
+	struct tegra_spi_client_data *cdata;
+	struct device_node *slave_np;
+
+	slave_np = spi->dev.of_node;
+	if (!slave_np) {
+		dev_dbg(&spi->dev, "device node not found\n");
+		return NULL;
+	}
+
+	cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
+	if (!cdata)
+		return NULL;
+
+	of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
+			     &cdata->tx_clk_tap_delay);
+	of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
+			     &cdata->rx_clk_tap_delay);
+	return cdata;
+}
+
+static void tegra_spi_cleanup(struct spi_device *spi)
+{
+	struct tegra_spi_client_data *cdata = spi->controller_data;
+
+	spi->controller_data = NULL;
+	if (spi->dev.of_node)
+		kfree(cdata);
+}
+
 static int tegra_spi_setup(struct spi_device *spi)
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
+	struct tegra_spi_client_data *cdata = spi->controller_data;
 	u32 val;
 	unsigned long flags;
 	int ret;
@@ -905,6 +958,11 @@ static int tegra_spi_setup(struct spi_device *spi)
 		spi->mode & SPI_CPHA ? "" : "~",
 		spi->max_speed_hz);
 
+	if (!cdata) {
+		cdata = tegra_spi_parse_cdata_dt(spi);
+		spi->controller_data = cdata;
+	}
+
 	ret = pm_runtime_get_sync(tspi->dev);
 	if (ret < 0) {
 		dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
@@ -1034,6 +1092,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
 			reset_control_assert(tspi->rst);
 			udelay(2);
 			reset_control_deassert(tspi->rst);
+			tspi->last_used_cs = master->num_chipselect + 1;
 			goto complete_xfer;
 		}
 
@@ -1351,6 +1410,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 	tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
 	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
+	tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
+	tspi->last_used_cs = master->num_chipselect + 1;
 	pm_runtime_put(&pdev->dev);
 	ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
 				   tegra_spi_isr_thread, IRQF_ONESHOT,
@@ -1423,6 +1484,8 @@ static int tegra_spi_resume(struct device *dev)
 		return ret;
 	}
 	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
+	tspi->last_used_cs = master->num_chipselect + 1;
 	pm_runtime_put(dev);
 
 	return spi_master_resume(master);
-- 
2.7.4


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
  2019-05-14  5:03 ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
@ 2019-05-14  9:33   ` Jon Hunter
  2019-05-14 17:18     ` Sowjanya Komatineni
  2019-05-15 11:18   ` Applied "spi: tegra114: add support for gpio based CS" to the spi tree Mark Brown
  1 sibling, 1 reply; 18+ messages in thread
From: Jon Hunter @ 2019-05-14  9:33 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, ldewangan, broonie
  Cc: linux-tegra, linux-kernel, linux-spi


On 14/05/2019 06:03, Sowjanya Komatineni wrote:
> This patch adds support for GPIO based CS control through SPI core
> function spi_set_cs.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Can you elaborate on the use-case where this is needed? I am curious
what platforms are using this and why they would not use the dedicated
CS signals.

Cheers
Jon

-- 
nvpublic

^ permalink raw reply	[flat|nested] 18+ messages in thread

* RE: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
  2019-05-14  9:33   ` Jon Hunter
@ 2019-05-14 17:18     ` Sowjanya Komatineni
  2019-05-14 17:31       ` Jon Hunter
  2019-05-15  9:35       ` Mark Brown
  0 siblings, 2 replies; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-14 17:18 UTC (permalink / raw)
  To: Jonathan Hunter, thierry.reding, Laxman Dewangan, broonie,
	Krishna Yarlagadda
  Cc: linux-tegra, linux-kernel, linux-spi

> Subject: Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS

> On 14/05/2019 06:03, Sowjanya Komatineni wrote:
> > This patch adds support for GPIO based CS control through SPI core 
> > function spi_set_cs.
> > 
> > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> Can you elaborate on the use-case where this is needed? I am curious what platforms are using this and why they would not use the dedicated CS signals.
>
> Cheers
> Jon

Tegra SPI doesn’t support inter byte delay directly to meet some SPI slave requirements.
So we use GPIO control CS in parallel with a dummy HW CS and use inactive cycles delay of SPI controller to mimic inter byte delay.

Currently we don’t have specific SPI slave on upstream supported platforms but considering raspberry PI header where SPI I/F is exposed to pins it allows user to connect any SPI slave and this helps for some slaves that need specific inter byte delay.

Thanks
sowjanya

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
  2019-05-14 17:18     ` Sowjanya Komatineni
@ 2019-05-14 17:31       ` Jon Hunter
  2019-05-15  9:35       ` Mark Brown
  1 sibling, 0 replies; 18+ messages in thread
From: Jon Hunter @ 2019-05-14 17:31 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, Laxman Dewangan, broonie,
	Krishna Yarlagadda
  Cc: linux-tegra, linux-kernel, linux-spi


On 14/05/2019 18:18, Sowjanya Komatineni wrote:
>> Subject: Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
> 
>> On 14/05/2019 06:03, Sowjanya Komatineni wrote:
>>> This patch adds support for GPIO based CS control through SPI core 
>>> function spi_set_cs.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> Can you elaborate on the use-case where this is needed? I am curious what platforms are using this and why they would not use the dedicated CS signals.
>>
>> Cheers
>> Jon
> 
> Tegra SPI doesn’t support inter byte delay directly to meet some SPI slave requirements.
> So we use GPIO control CS in parallel with a dummy HW CS and use inactive cycles delay of SPI controller to mimic inter byte delay.
> 
> Currently we don’t have specific SPI slave on upstream supported platforms but considering raspberry PI header where SPI I/F is exposed to pins it allows user to connect any SPI slave and this helps for some slaves that need specific inter byte delay.

Maybe add these details to the commit message so that it is clear what
the motivation for this is.

Thanks
Jon

-- 
nvpublic

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
  2019-05-14 17:18     ` Sowjanya Komatineni
  2019-05-14 17:31       ` Jon Hunter
@ 2019-05-15  9:35       ` Mark Brown
  2019-05-15 11:24         ` Sowjanya Komatineni
  1 sibling, 1 reply; 18+ messages in thread
From: Mark Brown @ 2019-05-15  9:35 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: Jonathan Hunter, thierry.reding, Laxman Dewangan,
	Krishna Yarlagadda, linux-tegra, linux-kernel, linux-spi

[-- Attachment #1: Type: text/plain, Size: 911 bytes --]

On Tue, May 14, 2019 at 05:18:48PM +0000, Sowjanya Komatineni wrote:

> Tegra SPI doesn’t support inter byte delay directly to meet some SPI slave requirements.
> So we use GPIO control CS in parallel with a dummy HW CS and use inactive cycles delay of SPI controller to mimic inter byte delay.

Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns.  Doing this makes your messages much
easier to read and reply to.

Please don't ignore review comments, people are generally making them
for a reason and are likely to have the same concerns if issues remain
unaddressed.  Having to repeat the same comments can get repetitive and
make people question the value of time spent reviewing.  If you disagree
with the review comments that's fine but you need to reply and discuss
your concerns so that the reviewer can understand your decisions.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Applied "spi: tegra114: add support for TX and RX trimmers" to the spi tree
  2019-05-14  5:03 ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni
@ 2019-05-15 11:18   ` Mark Brown
  2019-05-23  1:02   ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Nathan Chancellor
  1 sibling, 0 replies; 18+ messages in thread
From: Mark Brown @ 2019-05-15 11:18 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: broonie, jonathanh, ldewangan, linux-kernel, linux-spi,
	linux-tegra, Mark Brown, thierry.reding

The patch

   spi: tegra114: add support for TX and RX trimmers

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.3

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 318dacbd049b447a5b45290b39f1c889b9cbde4d Mon Sep 17 00:00:00 2001
From: Sowjanya Komatineni <skomatineni@nvidia.com>
Date: Mon, 13 May 2019 22:03:55 -0700
Subject: [PATCH] spi: tegra114: add support for TX and RX trimmers

Tegra SPI master controller has programmable trimmers to adjust the
data with respect to the clock.

These trimmers are programmed in TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY
fields of COMMAND2 register.

SPI TX trimmer is to adjust the outgoing data with respect to the
outgoing clock and SPI RX trimmer is to adjust the loopback clock with
respect to the incoming data from the slave device.

These trimmers vary based on trace lengths of the platform design for
each of the slaves on the SPI bus and optimal value programmed is from
the platform validation across PVT.

This patch adds support for configuring TX and RX clock delay trimmers
through the device tree properties.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-tegra114.c | 67 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 65 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index e59ff7c1cee6..253a7f182fc9 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -169,6 +169,11 @@ struct tegra_spi_soc_data {
 	bool has_intr_mask_reg;
 };
 
+struct tegra_spi_client_data {
+	int tx_clk_tap_delay;
+	int rx_clk_tap_delay;
+};
+
 struct tegra_spi_data {
 	struct device				*dev;
 	struct spi_master			*master;
@@ -208,8 +213,10 @@ struct tegra_spi_data {
 	u32					command1_reg;
 	u32					dma_control_reg;
 	u32					def_command1_reg;
+	u32					def_command2_reg;
 	u32					spi_cs_timing1;
 	u32					spi_cs_timing2;
+	u8					last_used_cs;
 
 	struct completion			xfer_completion;
 	struct spi_transfer			*curr_xfer;
@@ -770,10 +777,12 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 					bool is_single_xfer)
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
+	struct tegra_spi_client_data *cdata = spi->controller_data;
 	u32 speed = t->speed_hz;
 	u8 bits_per_word = t->bits_per_word;
-	u32 command1;
+	u32 command1, command2;
 	int req_mode;
+	u32 tx_tap = 0, rx_tap = 0;
 
 	if (speed != tspi->cur_speed) {
 		clk_set_rate(tspi->clk, speed);
@@ -836,7 +845,18 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 				command1 &= ~SPI_CS_SW_VAL;
 		}
 
-		tegra_spi_writel(tspi, 0, SPI_COMMAND2);
+		if (tspi->last_used_cs != spi->chip_select) {
+			if (cdata && cdata->tx_clk_tap_delay)
+				tx_tap = cdata->tx_clk_tap_delay;
+			if (cdata && cdata->rx_clk_tap_delay)
+				rx_tap = cdata->rx_clk_tap_delay;
+			command2 = SPI_TX_TAP_DELAY(tx_tap) |
+				   SPI_RX_TAP_DELAY(rx_tap);
+			if (command2 != tspi->def_command2_reg)
+				tegra_spi_writel(tspi, command2, SPI_COMMAND2);
+			tspi->last_used_cs = spi->chip_select;
+		}
+
 	} else {
 		command1 = tspi->command1_reg;
 		command1 &= ~SPI_BIT_LENGTH(~0);
@@ -892,9 +912,42 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi,
 	return ret;
 }
 
+static struct tegra_spi_client_data
+	*tegra_spi_parse_cdata_dt(struct spi_device *spi)
+{
+	struct tegra_spi_client_data *cdata;
+	struct device_node *slave_np;
+
+	slave_np = spi->dev.of_node;
+	if (!slave_np) {
+		dev_dbg(&spi->dev, "device node not found\n");
+		return NULL;
+	}
+
+	cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
+	if (!cdata)
+		return NULL;
+
+	of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
+			     &cdata->tx_clk_tap_delay);
+	of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
+			     &cdata->rx_clk_tap_delay);
+	return cdata;
+}
+
+static void tegra_spi_cleanup(struct spi_device *spi)
+{
+	struct tegra_spi_client_data *cdata = spi->controller_data;
+
+	spi->controller_data = NULL;
+	if (spi->dev.of_node)
+		kfree(cdata);
+}
+
 static int tegra_spi_setup(struct spi_device *spi)
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
+	struct tegra_spi_client_data *cdata = spi->controller_data;
 	u32 val;
 	unsigned long flags;
 	int ret;
@@ -905,6 +958,11 @@ static int tegra_spi_setup(struct spi_device *spi)
 		spi->mode & SPI_CPHA ? "" : "~",
 		spi->max_speed_hz);
 
+	if (!cdata) {
+		cdata = tegra_spi_parse_cdata_dt(spi);
+		spi->controller_data = cdata;
+	}
+
 	ret = pm_runtime_get_sync(tspi->dev);
 	if (ret < 0) {
 		dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
@@ -1034,6 +1092,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
 			reset_control_assert(tspi->rst);
 			udelay(2);
 			reset_control_deassert(tspi->rst);
+			tspi->last_used_cs = master->num_chipselect + 1;
 			goto complete_xfer;
 		}
 
@@ -1351,6 +1410,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 	tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
 	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
+	tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
+	tspi->last_used_cs = master->num_chipselect + 1;
 	pm_runtime_put(&pdev->dev);
 	ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
 				   tegra_spi_isr_thread, IRQF_ONESHOT,
@@ -1423,6 +1484,8 @@ static int tegra_spi_resume(struct device *dev)
 		return ret;
 	}
 	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
+	tspi->last_used_cs = master->num_chipselect + 1;
 	pm_runtime_put(dev);
 
 	return spi_master_resume(master);
-- 
2.20.1


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Applied "spi: tegra114: add support for HW CS timing" to the spi tree
  2019-05-14  5:03 ` [PATCH V5 3/4] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
@ 2019-05-15 11:18   ` Mark Brown
  0 siblings, 0 replies; 18+ messages in thread
From: Mark Brown @ 2019-05-15 11:18 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: broonie, jonathanh, ldewangan, linux-kernel, linux-spi,
	linux-tegra, Mark Brown, thierry.reding

The patch

   spi: tegra114: add support for HW CS timing

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.3

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 9b76ef39b7fbc2ddb0869725f9745a402d93cce5 Mon Sep 17 00:00:00 2001
From: Sowjanya Komatineni <skomatineni@nvidia.com>
Date: Mon, 13 May 2019 22:03:54 -0700
Subject: [PATCH] spi: tegra114: add support for HW CS timing

This patch implements set_cs_timing SPI controller method to allow
SPI client driver to configure device specific SPI CS timings.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-tegra114.c | 48 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 0cb0932d32fd..e59ff7c1cee6 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -95,8 +95,10 @@
 		(reg = (((val) & 0x1) << ((cs) * 8 + 5)) |	\
 			((reg) & ~(1 << ((cs) * 8 + 5))))
 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)		\
-		(reg = (((val) & 0xF) << ((cs) * 8)) |		\
-			((reg) & ~(0xF << ((cs) * 8))))
+		(reg = (((val) & 0x1F) << ((cs) * 8)) |		\
+			((reg) & ~(0x1F << ((cs) * 8))))
+#define MAX_SETUP_HOLD_CYCLES			16
+#define MAX_INACTIVE_CYCLES			32
 
 #define SPI_TRANS_STATUS			0x010
 #define SPI_BLK_CNT(val)			(((val) >> 0) & 0xFFFF)
@@ -206,6 +208,8 @@ struct tegra_spi_data {
 	u32					command1_reg;
 	u32					dma_control_reg;
 	u32					def_command1_reg;
+	u32					spi_cs_timing1;
+	u32					spi_cs_timing2;
 
 	struct completion			xfer_completion;
 	struct spi_transfer			*curr_xfer;
@@ -723,6 +727,43 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 	dma_release_channel(dma_chan);
 }
 
+static void tegra_spi_set_hw_cs_timing(struct spi_device *spi, u8 setup_dly,
+				       u8 hold_dly, u8 inactive_dly)
+{
+	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
+	u32 setup_hold;
+	u32 spi_cs_timing;
+	u32 inactive_cycles;
+	u8 cs_state;
+
+	setup_dly = min_t(u8, setup_dly, MAX_SETUP_HOLD_CYCLES);
+	hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES);
+	if (setup_dly && hold_dly) {
+		setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
+		spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
+						  spi->chip_select,
+						  setup_hold);
+		if (tspi->spi_cs_timing1 != spi_cs_timing) {
+			tspi->spi_cs_timing1 = spi_cs_timing;
+			tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
+		}
+	}
+
+	inactive_cycles = min_t(u8, inactive_dly, MAX_INACTIVE_CYCLES);
+	if (inactive_cycles)
+		inactive_cycles--;
+	cs_state = inactive_cycles ? 0 : 1;
+	spi_cs_timing = tspi->spi_cs_timing2;
+	SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
+					  cs_state);
+	SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
+				       inactive_cycles);
+	if (tspi->spi_cs_timing2 != spi_cs_timing) {
+		tspi->spi_cs_timing2 = spi_cs_timing;
+		tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
+	}
+}
+
 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 					struct spi_transfer *t,
 					bool is_first_of_msg,
@@ -1232,6 +1273,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 	master->setup = tegra_spi_setup;
 	master->transfer_one_message = tegra_spi_transfer_one_message;
+	master->set_cs_timing = tegra_spi_set_hw_cs_timing;
 	master->num_chipselect = MAX_CHIP_SELECT;
 	master->auto_runtime_pm = true;
 	bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
@@ -1307,6 +1349,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	reset_control_deassert(tspi->rst);
 	tspi->def_command1_reg  = SPI_M_S;
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
+	tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
+	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
 	pm_runtime_put(&pdev->dev);
 	ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
 				   tegra_spi_isr_thread, IRQF_ONESHOT,
-- 
2.20.1


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Applied "spi: tegra114: add support for gpio based CS" to the spi tree
  2019-05-14  5:03 ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
  2019-05-14  9:33   ` Jon Hunter
@ 2019-05-15 11:18   ` Mark Brown
  1 sibling, 0 replies; 18+ messages in thread
From: Mark Brown @ 2019-05-15 11:18 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: broonie, jonathanh, ldewangan, linux-kernel, linux-spi,
	linux-tegra, Mark Brown, thierry.reding

The patch

   spi: tegra114: add support for gpio based CS

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.3

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 63c1440596ff0a34efec491f41832c2c9ea01857 Mon Sep 17 00:00:00 2001
From: Sowjanya Komatineni <skomatineni@nvidia.com>
Date: Mon, 13 May 2019 22:03:52 -0700
Subject: [PATCH] spi: tegra114: add support for gpio based CS

This patch adds support for GPIO based CS control through SPI core
function spi_set_cs.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-tegra114.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index b1f31bb16659..f47417dd9edb 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -776,6 +776,10 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 		} else
 			tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 
+		/* GPIO based chip select control */
+		if (spi->cs_gpiod)
+			gpiod_set_value(spi->cs_gpiod, 1);
+
 		command1 |= SPI_CS_SW_HW;
 		if (spi->mode & SPI_CS_HIGH)
 			command1 |= SPI_CS_SW_VAL;
@@ -864,6 +868,10 @@ static int tegra_spi_setup(struct spi_device *spi)
 	}
 
 	spin_lock_irqsave(&tspi->lock, flags);
+	/* GPIO based chip select control */
+	if (spi->cs_gpiod)
+		gpiod_set_value(spi->cs_gpiod, 0);
+
 	val = tspi->def_command1_reg;
 	if (spi->mode & SPI_CS_HIGH)
 		val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
@@ -893,6 +901,10 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 	int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
 
+	/* GPIO based chip select control */
+	if (spi->cs_gpiod)
+		gpiod_set_value(spi->cs_gpiod, 0);
+
 	if (cs_val)
 		tspi->command1_reg |= SPI_CS_SW_VAL;
 	else
@@ -1199,6 +1211,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
 		master->max_speed_hz = 25000000; /* 25MHz */
 
 	/* the spi->mode bits understood by this driver: */
+	master->use_gpio_descriptors = true;
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
 			    SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
-- 
2.20.1


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Applied "spi: tegra114: add support for hw based cs" to the spi tree
  2019-05-14  5:03 ` [PATCH V5 2/4] spi: tegra114: add support for hw based cs Sowjanya Komatineni
@ 2019-05-15 11:18   ` Mark Brown
  0 siblings, 0 replies; 18+ messages in thread
From: Mark Brown @ 2019-05-15 11:18 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: broonie, jonathanh, ldewangan, linux-kernel, linux-spi,
	linux-tegra, Mark Brown, thierry.reding

The patch

   spi: tegra114: add support for hw based cs

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.3

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 1bf9f3c9232d08651aa6990001e7b042c95303dc Mon Sep 17 00:00:00 2001
From: Sowjanya Komatineni <skomatineni@nvidia.com>
Date: Mon, 13 May 2019 22:03:53 -0700
Subject: [PATCH] spi: tegra114: add support for hw based cs

Tegra SPI controller supports both HW and SW based CS control
for SPI transfers.

This patch adds support for HW based CS control where CS is driven
to active state during the transfer and is driven inactive at the
end of the transfer directly by the HW.

This patch enables the use of HW based CS only for single transfers
without cs_change request.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-tegra114.c | 39 ++++++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index f47417dd9edb..0cb0932d32fd 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -193,6 +193,7 @@ struct tegra_spi_data {
 	unsigned				dma_buf_size;
 	unsigned				max_buf_size;
 	bool					is_curr_dma_xfer;
+	bool					use_hw_based_cs;
 
 	struct completion			rx_dma_complete;
 	struct completion			tx_dma_complete;
@@ -723,7 +724,9 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 }
 
 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
-		struct spi_transfer *t, bool is_first_of_msg)
+					struct spi_transfer *t,
+					bool is_first_of_msg,
+					bool is_single_xfer)
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 	u32 speed = t->speed_hz;
@@ -780,11 +783,17 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 		if (spi->cs_gpiod)
 			gpiod_set_value(spi->cs_gpiod, 1);
 
-		command1 |= SPI_CS_SW_HW;
-		if (spi->mode & SPI_CS_HIGH)
-			command1 |= SPI_CS_SW_VAL;
-		else
-			command1 &= ~SPI_CS_SW_VAL;
+		if (is_single_xfer && !(t->cs_change)) {
+			tspi->use_hw_based_cs = true;
+			command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
+		} else {
+			tspi->use_hw_based_cs = false;
+			command1 |= SPI_CS_SW_HW;
+			if (spi->mode & SPI_CS_HIGH)
+				command1 |= SPI_CS_SW_VAL;
+			else
+				command1 &= ~SPI_CS_SW_VAL;
+		}
 
 		tegra_spi_writel(tspi, 0, SPI_COMMAND2);
 	} else {
@@ -905,11 +914,14 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
 	if (spi->cs_gpiod)
 		gpiod_set_value(spi->cs_gpiod, 0);
 
-	if (cs_val)
-		tspi->command1_reg |= SPI_CS_SW_VAL;
-	else
-		tspi->command1_reg &= ~SPI_CS_SW_VAL;
-	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	if (!tspi->use_hw_based_cs) {
+		if (cs_val)
+			tspi->command1_reg |= SPI_CS_SW_VAL;
+		else
+			tspi->command1_reg &= ~SPI_CS_SW_VAL;
+		tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	}
+
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 }
 
@@ -936,16 +948,19 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
 	struct spi_device *spi = msg->spi;
 	int ret;
 	bool skip = false;
+	int single_xfer;
 
 	msg->status = 0;
 	msg->actual_length = 0;
 
+	single_xfer = list_is_singular(&msg->transfers);
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 		u32 cmd1;
 
 		reinit_completion(&tspi->xfer_completion);
 
-		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
+		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
+						    single_xfer);
 
 		if (!xfer->len) {
 			ret = 0;
-- 
2.20.1


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
  2019-05-15  9:35       ` Mark Brown
@ 2019-05-15 11:24         ` Sowjanya Komatineni
  2019-05-15 11:29           ` Mark Brown
  0 siblings, 1 reply; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-15 11:24 UTC (permalink / raw)
  To: Mark Brown
  Cc: Jonathan Hunter, thierry.reding, Laxman Dewangan,
	Krishna Yarlagadda, linux-tegra, linux-kernel, linux-spi

> > Tegra SPI doesn’t support inter byte delay directly to meet some SPI slave requirements.
> > So we use GPIO control CS in parallel with a dummy HW CS and use inactive cycles delay of SPI controller to mimic inter byte delay.

> Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns.  Doing this makes your messages much
easier to read and reply to.

I did changed but looks like it didn't made diff. Will try with different email client.

> Please don't ignore review comments, people are generally making them
for a reason and are likely to have the same concerns if issues remain
unaddressed.  Having to repeat the same comments can get repetitive and
make people question the value of time spent reviewing.  If you disagree
with the review comments that's fine but you need to reply and discuss
your concerns so that the reviewer can understand your decisions.


If you are referring to comment from Jon on updating commit, I didn't ignored. I am just waiting if any more comments from you or others before posting updated patch. 

But I see you applied patch now. So how should I post with updated commit?

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
  2019-05-15 11:24         ` Sowjanya Komatineni
@ 2019-05-15 11:29           ` Mark Brown
       [not found]             ` <BYAPR12MB3398528B86D3DE9CC3AA6D85C2090@BYAPR12MB3398.namprd12.prod.outlook.com>
  0 siblings, 1 reply; 18+ messages in thread
From: Mark Brown @ 2019-05-15 11:29 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: Jonathan Hunter, thierry.reding, Laxman Dewangan,
	Krishna Yarlagadda, linux-tegra, linux-kernel, linux-spi

[-- Attachment #1: Type: text/plain, Size: 1599 bytes --]

On Wed, May 15, 2019 at 11:24:22AM +0000, Sowjanya Komatineni wrote:

> > Please fix your mail client to word wrap within paragraphs at something
> substantially less than 80 columns.  Doing this makes your messages much
> easier to read and reply to.

> I did changed but looks like it didn't made diff. Will try with different email client.

Yeah, the behaviour is exactly the same - it's not only not wrapping
your content but also reflowing quoted content.

> > Please don't ignore review comments, people are generally making them
> for a reason and are likely to have the same concerns if issues remain
> unaddressed.  Having to repeat the same comments can get repetitive and
> make people question the value of time spent reviewing.  If you disagree
> with the review comments that's fine but you need to reply and discuss
> your concerns so that the reviewer can understand your decisions.

> If you are referring to comment from Jon on updating commit, I didn't ignored. I am just waiting if any more comments from you or others before posting updated patch. 

That was more about the continuing issues with mail formatting.

> But I see you applied patch now. So how should I post with updated commit?

No, it's fine.  It would have been better to have a clearer commit
message but I think the usage makes it reasonably clear in the final
code why that was done and honestly "the hardware doesn't support all
the features we need to properly control devices" is an extremely common
reason for using GPIO chip selects even when hardware support is
available.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
       [not found]             ` <BYAPR12MB3398528B86D3DE9CC3AA6D85C2090@BYAPR12MB3398.namprd12.prod.outlook.com>
@ 2019-05-15 11:42               ` Mark Brown
  0 siblings, 0 replies; 18+ messages in thread
From: Mark Brown @ 2019-05-15 11:42 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: Jonathan Hunter, thierry.reding, Laxman Dewangan,
	Krishna Yarlagadda, linux-tegra, linux-kernel, linux-spi

[-- Attachment #1: Type: text/plain, Size: 417 bytes --]

On Wed, May 15, 2019 at 11:40:41AM +0000, Sowjanya Komatineni wrote:
> I tried few settings before sending V5 too but didn't made diff.
> Will try with different email client.
> 
> What email client are you using?

I personally use mutt.  I know people also use things like Thunderbird
and Evolution successfully.  There should be other people at nVidia you
can ask about how they get things set up I guess?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers
  2019-05-14  5:03 ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni
  2019-05-15 11:18   ` Applied "spi: tegra114: add support for TX and RX trimmers" to the spi tree Mark Brown
@ 2019-05-23  1:02   ` Nathan Chancellor
  2019-05-23  1:10     ` Sowjanya Komatineni
  1 sibling, 1 reply; 18+ messages in thread
From: Nathan Chancellor @ 2019-05-23  1:02 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: thierry.reding, jonathanh, ldewangan, broonie, linux-tegra,
	linux-kernel, linux-spi

Hi Sowjanya,

On Mon, May 13, 2019 at 10:03:55PM -0700, Sowjanya Komatineni wrote:
> Tegra SPI master controller has programmable trimmers to adjust the
> data with respect to the clock.
> 
> These trimmers are programmed in TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY
> fields of COMMAND2 register.
> 
> SPI TX trimmer is to adjust the outgoing data with respect to the
> outgoing clock and SPI RX trimmer is to adjust the loopback clock with
> respect to the incoming data from the slave device.
> 
> These trimmers vary based on trace lengths of the platform design for
> each of the slaves on the SPI bus and optimal value programmed is from
> the platform validation across PVT.
> 
> This patch adds support for configuring TX and RX clock delay trimmers
> through the device tree properties.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/spi/spi-tegra114.c | 67 ++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 65 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
> index e59ff7c1cee6..253a7f182fc9 100644
> --- a/drivers/spi/spi-tegra114.c
> +++ b/drivers/spi/spi-tegra114.c

<snip>

> +static void tegra_spi_cleanup(struct spi_device *spi)
> +{
> +	struct tegra_spi_client_data *cdata = spi->controller_data;
> +
> +	spi->controller_data = NULL;
> +	if (spi->dev.of_node)
> +		kfree(cdata);
> +}
> +

This function is not called anywhere and it is marked as static so it
triggers an unused function warning. Was that intentional?

drivers/spi/spi-tegra114.c:938:13: warning: unused function 'tegra_spi_cleanup' [-Wunused-function]
static void tegra_spi_cleanup(struct spi_device *spi)
            ^
1 warning generated.

Cheers,
Nathan

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers
  2019-05-23  1:02   ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Nathan Chancellor
@ 2019-05-23  1:10     ` Sowjanya Komatineni
  0 siblings, 0 replies; 18+ messages in thread
From: Sowjanya Komatineni @ 2019-05-23  1:10 UTC (permalink / raw)
  To: Nathan Chancellor
  Cc: thierry.reding, jonathanh, ldewangan, broonie, linux-tegra,
	linux-kernel, linux-spi

Hi Nathan

Thanks for finding it. I missed to set it to master cleanup when I 
updated the patch.

Will send the patch fixing this.

Thanks

Sowjanya

On 5/22/19 6:02 PM, Nathan Chancellor wrote:
> Hi Sowjanya,
>
> On Mon, May 13, 2019 at 10:03:55PM -0700, Sowjanya Komatineni wrote:
>> Tegra SPI master controller has programmable trimmers to adjust the
>> data with respect to the clock.
>>
>> These trimmers are programmed in TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY
>> fields of COMMAND2 register.
>>
>> SPI TX trimmer is to adjust the outgoing data with respect to the
>> outgoing clock and SPI RX trimmer is to adjust the loopback clock with
>> respect to the incoming data from the slave device.
>>
>> These trimmers vary based on trace lengths of the platform design for
>> each of the slaves on the SPI bus and optimal value programmed is from
>> the platform validation across PVT.
>>
>> This patch adds support for configuring TX and RX clock delay trimmers
>> through the device tree properties.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>>   drivers/spi/spi-tegra114.c | 67 ++++++++++++++++++++++++++++++++++++++++++++--
>>   1 file changed, 65 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
>> index e59ff7c1cee6..253a7f182fc9 100644
>> --- a/drivers/spi/spi-tegra114.c
>> +++ b/drivers/spi/spi-tegra114.c
> <snip>
>
>> +static void tegra_spi_cleanup(struct spi_device *spi)
>> +{
>> +	struct tegra_spi_client_data *cdata = spi->controller_data;
>> +
>> +	spi->controller_data = NULL;
>> +	if (spi->dev.of_node)
>> +		kfree(cdata);
>> +}
>> +
> This function is not called anywhere and it is marked as static so it
> triggers an unused function warning. Was that intentional?
>
> drivers/spi/spi-tegra114.c:938:13: warning: unused function 'tegra_spi_cleanup' [-Wunused-function]
> static void tegra_spi_cleanup(struct spi_device *spi)
>              ^
> 1 warning generated.
>
> Cheers,
> Nathan

^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2019-05-23  1:10 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-14  5:03 [PATCH V5 0/4] additional features to Tegra SPI Sowjanya Komatineni
2019-05-14  5:03 ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
2019-05-14  9:33   ` Jon Hunter
2019-05-14 17:18     ` Sowjanya Komatineni
2019-05-14 17:31       ` Jon Hunter
2019-05-15  9:35       ` Mark Brown
2019-05-15 11:24         ` Sowjanya Komatineni
2019-05-15 11:29           ` Mark Brown
     [not found]             ` <BYAPR12MB3398528B86D3DE9CC3AA6D85C2090@BYAPR12MB3398.namprd12.prod.outlook.com>
2019-05-15 11:42               ` Mark Brown
2019-05-15 11:18   ` Applied "spi: tegra114: add support for gpio based CS" to the spi tree Mark Brown
2019-05-14  5:03 ` [PATCH V5 2/4] spi: tegra114: add support for hw based cs Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for hw based cs" to the spi tree Mark Brown
2019-05-14  5:03 ` [PATCH V5 3/4] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for HW CS timing" to the spi tree Mark Brown
2019-05-14  5:03 ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for TX and RX trimmers" to the spi tree Mark Brown
2019-05-23  1:02   ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Nathan Chancellor
2019-05-23  1:10     ` Sowjanya Komatineni

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