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From: Michael Ellerman <michael@ellerman.id.au>
To: akepner@sgi.com
Cc: James Bottomley <James.Bottomley@HansenPartnership.com>,
	Grant Grundler <grundler@parisc-linux.org>,
	Tony Luck <tony.luck@intel.com>,
	Jesse Barnes <jbarnes@virtuousgeek.org>,
	Jes Sorensen <jes@sgi.com>,
	Randy Dunlap <randy.dunlap@oracle.com>,
	Roland Dreier <rdreier@cisco.com>,
	David Miller <davem@davemloft.net>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	linux-kernel@vger.kernel.org, Mark Nelson <mdnelson@au1.ibm.com>
Subject: Re: [PATCH 1/3 v3] dma: document dma_{un}map_{single|sg}_attrs() interface
Date: Fri, 14 Mar 2008 15:30:29 +1100	[thread overview]
Message-ID: <1205469029.7414.18.camel@concordia.ozlabs.ibm.com> (raw)
In-Reply-To: <20080312011954.GN12370@sgi.com>

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On Tue, 2008-03-11 at 18:19 -0700, akepner@sgi.com wrote:
> I have a new proposal for the documentation portion of this 
> patchset. The code changes essentially amount to 
> s/DMA_ATTR_SYNC_ON_WRITE/DMA_ATTR_BARRIER/ so thought I'd send 
> just the doc change for comments now.
> 
> The description of the DMA_ATTR_BARRIER is now very short and 
> generic - no particular architecture is even mentioned. I can add 
> a sentence or two near the architecture-specific changes in 
> arch/ia64/sn/pci/pci_dma.c about why the implementation works 
> on ia64/sn, etc.

I like this better, sorry to keep nitpicking, but just a few comments
below ..

> diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt
> index e69de29..a4106ec 100644
> --- a/Documentation/DMA-attributes.txt
> +++ b/Documentation/DMA-attributes.txt
> @@ -0,0 +1,24 @@
> +			DMA attributes
> +			==============
> +
> +This document describes the semantics of the DMA attributes that are 
> +defined in linux/dma-attrs.h. 
> +
> +DMA_ATTR_BARRIER
> +----------------
> +
> +DMA_ATTR_BARRIER is a barrier attribute for DMA.  DMA to a memory 
> +region with the DMA_ATTR_BARRIER attribute forces all pending DMA 
> +writes to complete, and thus provides a mechanism to strictly order 
> +DMA from a device across all intervening busses and bridges.  This 
> +barrier is not specific to a particular type of interconnect, it 
> +applies to the system as a whole, and so its implementation must 
> +account for the idiosyncracies of the system all the way from the 
> +DMA device to memory. 

You say a "DMA to a memory region with the DMA_ATTR_BARRIER attribute
forces all pending DMA writes to complete". Does it force _all_ DMA
writes to complete, or just writes to the region, or just writes coming
from devices? What if something is writing to a device?

Does DMA_ATTR_BARRIER have any effect on reads?

cheers

-- 
Michael Ellerman
OzLabs, IBM Australia Development Lab

wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)

We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person

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  parent reply	other threads:[~2008-03-14  4:32 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-02-28  3:24 akepner
2008-02-29  2:45 ` Michael Ellerman
2008-02-29 18:25   ` Grant Grundler
2008-02-29 18:37     ` James Bottomley
2008-03-01  2:56       ` Benjamin Herrenschmidt
2008-03-01  3:11         ` Jesse Barnes
2008-03-01  7:18         ` Grant Grundler
2008-03-05 18:13       ` akepner
2008-03-05 19:02         ` Jesse Barnes
2008-03-06  6:01         ` Michael Ellerman
2008-03-12  1:19           ` akepner
2008-03-14  4:13             ` Grant Grundler
2008-03-14  4:30             ` Michael Ellerman [this message]
2008-03-14  5:21               ` Grant Grundler
2008-03-14 16:40                 ` Jesse Barnes
2008-03-18  1:08                 ` Michael Ellerman
2008-03-20  0:32               ` akepner
2008-02-29 21:23   ` akepner

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