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From: Alexandre Torgue <alexandre.torgue@st.com>
To: Biao Huang <biao.huang@mediatek.com>, Jose Abreu <joabreu@synopsys.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	<netdev@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <yt.shen@mediatek.com>,
	<jianguo.zhang@mediatek.comi>, <boon.leong.ong@intel.com>
Subject: Re: [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue
Date: Fri, 24 May 2019 09:07:28 +0200	[thread overview]
Message-ID: <120eba91-6d7f-1365-6b1c-e8365e54136c@st.com> (raw)
In-Reply-To: <1558679169-26752-3-git-send-email-biao.huang@mediatek.com>

Hi Biao

On 5/24/19 8:26 AM, Biao Huang wrote:
> The specific clk_csr value can be zero, and
> stmmac_clk is necessary for MDC clock which can be set dynamically.
> So, change the condition from plat->clk_csr to plat->stmmac_clk to
> fix clk_csr can't be zero issue.
> 
> Fixes: cd7201f477b9 ("stmmac: MDC clock dynamically based on the csr clock input")
> Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> ---
>   drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |    6 +++---
>   .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |    5 ++++-
>   2 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 06487a6..b2feb6c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -4380,10 +4380,10 @@ int stmmac_dvr_probe(struct device *device,
>   	 * set the MDC clock dynamically according to the csr actual
>   	 * clock input.
>   	 */
> -	if (!priv->plat->clk_csr)
> -		stmmac_clk_csr_set(priv);
> -	else
> +	if (priv->plat->clk_csr >= 0)
>   		priv->clk_csr = priv->plat->clk_csr;
> +	else
> +		stmmac_clk_csr_set(priv);
>   
>   	stmmac_check_pcs_mode(priv);
>   
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> index 3031f2b..f45bfbe 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> @@ -408,7 +408,10 @@ struct plat_stmmacenet_data *
>   	/* Default to phy auto-detection */
>   	plat->phy_addr = -1;
>   
> -	/* Get clk_csr from device tree */
> +	/* Default to get clk_csr from stmmac_clk_crs_set(),
> +	 * or get clk_csr from device tree.
> +	 */
> +	plat->clk_csr = -1;
>   	of_property_read_u32(np, "clk_csr", &plat->clk_csr);
>   
>   	/* "snps,phy-addr" is not a standard property. Mark it as deprecated
> 

Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>

thanks
Alex

  reply	other threads:[~2019-05-24  7:07 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-24  6:26 [v4, PATCH 0/3] fix some bugs in stmmac Biao Huang
2019-05-24  6:26 ` [v4, PATCH 1/3] net: stmmac: update rx tail pointer register to fix rx dma hang issue Biao Huang
2019-05-24  6:26 ` [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue Biao Huang
2019-05-24  7:07   ` Alexandre Torgue [this message]
2019-05-24  6:26 ` [v4, PATCH 3/3] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Biao Huang
2019-05-25 18:02 ` [v4, PATCH 0/3] fix some bugs in stmmac David Miller

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