Re: [PATCH -v2] x86, acpi: Handle xapic/x2apic entries in MADT at same time

[Suresh Siddha <suresh.b.siddha@intel.com>]

On Thu, 2011-01-27 at 19:09 -0800, Yinghai Lu wrote:
> One system have mixing xapic and x2apic entries in MADT and SRAT.
> BIOS guys insist that ACPI 4.0 SPEC said so, if apic id < 255, even
> the cpus are with x2apic mode pre-enabled, still need to use xapic entries
> instead of x2apic entries.

true. thats what the spec says.

> on 8 socket system with x2apic pre-enabled, will get out of order sequence:
> CPU0: socket0, core0, thread0.
> CPU1 - CPU 40: socket 4 - socket 7, thread 0
> CPU41 - CPU 80: socket 4 - socket 7, thread 1
> CPU81 - CPU 119: socket 0 - socket 3, thread 0
> CPU120 - CPU 159: socket 0 - socket 3, thread 1
> 
> so max_cpus=80 will not get all thread0 now.
> 
> Need to handle every entry in MADT at same time with xapic and x2apic.
> so we can honor sequence in MADT.

hmm few things.

So is your bios listing like this:

xapic entries for all thread-0
x2apic entries for all thread-0
xapic entries for all thread-1
x2apic entries for all thread-1

What happens if some other bios lists like:

all xapic entries
followed by all x2apic entries

or

all x2apic entries
followed by all x2apic entries

I am not sure if there is a strict recommendation by Intel bios writers
guide to list all thread-0 first followed by thread-1. Even if there is
a strict recommendation like that, I am sure there will be some bios's
that don't follow the rules.

Anyways two things.

a) I don't want to complicate the code too much and still doesn't get
the desired behavior when some bios has a different silly ordering.

b) Also perhaps we need to make it more explicit. Like instead of
relying on the "maxcpus=n/2" to boot all thread-0's, we should say it
more explicitly like perhaps nosmt or noht (we used to have this kind of
option before).  Or is it even worth to bother about this, given that we
can boot all the cpu's and offline the SMT siblings.


> We can use max_cpus= command line to use thread0 in every core,
> because recent MADT always have all thread0 at first.
> Also it could make the cpu to node mapping more sane.
> 
> after patch will get
> CPU0 - CPU 79: socket 0 - socket 7, thread 0
> CPU80 - CPU 159: socket 0 - socket 7, thread 1
> 
> -v2: update some comments, and change to pass array pointer.
> 

thanks,
suresh