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From: Peter Zijlstra <peterz@infradead.org>
To: Robert Richter <robert.richter@amd.com>
Cc: Ingo Molnar <mingo@elte.hu>,
	Stephane Eranian <eranian@google.com>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 5/5] perf, x86: Add support for AMD family 15h core counters
Date: Wed, 02 Feb 2011 18:29:37 +0100	[thread overview]
Message-ID: <1296667777.26581.349.camel@laptop> (raw)
In-Reply-To: <20110202172419.GB5874@erda.amd.com>

On Wed, 2011-02-02 at 18:24 +0100, Robert Richter wrote:
> On 02.02.11 12:03:18, Peter Zijlstra wrote:
> > On Wed, 2011-02-02 at 17:41 +0100, Robert Richter wrote:
> > > +       unsigned int    eventsel;
> > > +       unsigned int    perfctr;
> > > +       unsigned int    *eventsel_map;
> > > +       unsigned int    *perfctr_map;
> > >         u64             (*event_map)(int);
> > >         int             max_events;
> > >         int             num_counters;
> > > @@ -323,11 +325,17 @@ again:
> > >  
> > >  static inline unsigned int x86_pmu_config_addr(int index)
> > >  {
> > > +       if (x86_pmu.eventsel_map)
> > > +               return x86_pmu.eventsel_map[index];
> > > +
> > >         return x86_pmu.eventsel + index;
> > >  }
> > >  
> > >  static inline unsigned int x86_pmu_event_addr(int index)
> > >  {
> > > +       if (x86_pmu.perfctr_map)
> > > +               return x86_pmu.perfctr_map[index];
> > > +
> > >         return x86_pmu.perfctr + index;
> > >  } 
> > 
> > Why this and not something like x86_pmu.perfctr + (index << 1)?
> > You could even use alternatives.
> 
> I was thinking about this. The main reason is the implementation of
> northbridge counters, the range is in MSRC001_02[47:40]. This would
> add more complexity then. Using a table would be something like
> 
> unsigned int eventsel_f15h[] = {
> 	MSR_F15H_PERF_CTL,
> 	MSR_F15H_PERF_CTL + 2,
> 	MSR_F15H_PERF_CTL + 4,
> 	MSR_F15H_PERF_CTL + 6,
> 	MSR_F15H_PERF_CTL + 8,
> 	MSR_F15H_PERF_CTL + 10,
> 	MSR_F15H_NB_PERF_CTL,
> 	MSR_F15H_NB_PERF_CTL + 2,
> 	MSR_F15H_NB_PERF_CTL + 6,
> 	MSR_F15H_NB_PERF_CTL + 8,
> };
> 
> We don't need to change the address generation for this. Otherwise we
> need to introduce more logic for the calculation.
> 
> Also, were could be potential easier implementations for fixed
> counters, BTS, P4, IBS, etc. But didn't look that close at it.
> 
> (Btw, I am not yet sure if NB counters shouldn't better start at index
> 16 or so to reserve space for perf counter expansion.)

Now that the NB PMU is completely separate from the core PMU, wouldn't
it make more sense to implement that as a separate entity just like the
intel uncore bits?


  reply	other threads:[~2011-02-02 17:28 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-02-02 16:40 [PATCH 0/5] perf, x86: " Robert Richter
2011-02-02 16:40 ` [PATCH 1/5] perf, x86: Use helper function in x86_pmu_enable_all() Robert Richter
2011-02-16 13:47   ` [tip:perf/core] " tip-bot for Robert Richter
2011-02-02 16:40 ` [PATCH 2/5] perf, x86: Calculate perfctr msr addresses in helper functions Robert Richter
2011-02-16 13:48   ` [tip:perf/core] " tip-bot for Robert Richter
2011-02-02 16:40 ` [PATCH 3/5] perf, x86: Add new AMD family 15h msrs to perfctr reservation code Robert Richter
2011-02-16 13:48   ` [tip:perf/core] " tip-bot for Robert Richter
2011-02-02 16:40 ` [PATCH 4/5] perf, x86: Store perfctr msr addresses in config_base/event_base Robert Richter
2011-02-16 13:48   ` [tip:perf/core] " tip-bot for Robert Richter
2011-02-02 16:41 ` [PATCH 5/5] perf, x86: Add support for AMD family 15h core counters Robert Richter
2011-02-02 17:03   ` Peter Zijlstra
2011-02-02 17:24     ` Robert Richter
2011-02-02 17:29       ` Peter Zijlstra [this message]
2011-02-02 22:44         ` Stephane Eranian
2011-02-03  9:00           ` Robert Richter
2011-02-03  9:38             ` Peter Zijlstra
2011-02-03 14:06               ` Robert Richter
2011-02-15 13:52                 ` [PATCH] " Robert Richter
2011-02-16 13:49                   ` [tip:perf/core] " tip-bot for Robert Richter
2011-02-02 20:38 ` [PATCH 0/5] perf, x86: " Stephane Eranian

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