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From: Jiang Liu <jiang.liu@linux.intel.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Randy Dunlap <rdunlap@infradead.org>,
	Yinghai Lu <yinghai@kernel.org>, Borislav Petkov <bp@alien8.de>,
	Dimitri Sivanich <sivanich@sgi.com>,
	x86@kernel.org, Jiang Liu <jiang.liu@linux.intel.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	David Cohen <david.a.cohen@linux.intel.com>,
	Sander Eikelenboom <linux@eikelenboom.it>,
	David Vrabel <david.vrabel@citrix.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Tony Luck <tony.luck@intel.com>, Joerg Roedel <joro@8bytes.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-acpi@vger.kernel.org
Subject: [Patch Part1 v7 20/38] x86/irq: Use hierarchy irqdomain to manage DMAR interrupts
Date: Tue, 20 Jan 2015 11:08:23 +0800	[thread overview]
Message-ID: <1421723321-8386-21-git-send-email-jiang.liu@linux.intel.com> (raw)
In-Reply-To: <1421723321-8386-1-git-send-email-jiang.liu@linux.intel.com>

Enhance DMAR code to support hierarchy irqdomain, it helps to make
the architecture more clear.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Link: http://lkml.kernel.org/r/1416894816-23245-21-git-send-email-jiang.liu@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/include/asm/hw_irq.h |    7 ++
 arch/x86/kernel/apic/msi.c    |  153 ++++++++++++++++++++++++++---------------
 2 files changed, 103 insertions(+), 57 deletions(-)

diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 270c432971f8..29f1dc162a24 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -122,6 +122,7 @@ enum irq_alloc_type {
 	X86_IRQ_ALLOC_TYPE_HPET,
 	X86_IRQ_ALLOC_TYPE_MSI,
 	X86_IRQ_ALLOC_TYPE_MSIX,
+	X86_IRQ_ALLOC_TYPE_DMAR,
 };
 
 struct irq_alloc_info {
@@ -154,6 +155,12 @@ struct irq_alloc_info {
 			struct IO_APIC_route_entry *ioapic_entry;
 		};
 #endif
+#ifdef	CONFIG_DMAR_TABLE
+		struct {
+			int		dmar_id;
+			void		*dmar_data;
+		};
+#endif
 	};
 };
 
diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
index 695c82bbd682..a24b803b199a 100644
--- a/arch/x86/kernel/apic/msi.c
+++ b/arch/x86/kernel/apic/msi.c
@@ -25,32 +25,6 @@
 
 static struct irq_domain *msi_default_domain;
 
-static void native_compose_msi_msg(struct irq_cfg *cfg, struct msi_msg *msg)
-{
-	msg->address_hi = MSI_ADDR_BASE_HI;
-
-	if (x2apic_enabled())
-		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
-
-	msg->address_lo =
-		MSI_ADDR_BASE_LO |
-		((apic->irq_dest_mode == 0) ?
-			MSI_ADDR_DEST_MODE_PHYSICAL :
-			MSI_ADDR_DEST_MODE_LOGICAL) |
-		((apic->irq_delivery_mode != dest_LowestPrio) ?
-			MSI_ADDR_REDIRECTION_CPU :
-			MSI_ADDR_REDIRECTION_LOWPRI) |
-		MSI_ADDR_DEST_ID(cfg->dest_apicid);
-
-	msg->data =
-		MSI_DATA_TRIGGER_EDGE |
-		MSI_DATA_LEVEL_ASSERT |
-		((apic->irq_delivery_mode != dest_LowestPrio) ?
-			MSI_DATA_DELIVERY_FIXED :
-			MSI_DATA_DELIVERY_LOWPRI) |
-		MSI_DATA_VECTOR(cfg->vector);
-}
-
 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
 {
 	struct irq_cfg *cfg = irqd_cfg(data);
@@ -87,6 +61,9 @@ static void msi_update_msg(struct msi_msg *msg, struct irq_data *irq_data)
 	msg->data |= MSI_DATA_VECTOR(cfg->vector);
 	msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
 	msg->address_lo |= MSI_ADDR_DEST_ID(cfg->dest_apicid);
+	if (x2apic_enabled())
+		msg->address_hi = MSI_ADDR_BASE_HI |
+				  MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
 }
 
 /*
@@ -196,59 +173,121 @@ static int
 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
 		      bool force)
 {
-	struct irq_cfg *cfg = irqd_cfg(data);
-	unsigned int dest, irq = data->irq;
+	struct irq_data *parent = data->parent_data;
 	struct msi_msg msg;
 	int ret;
 
-	ret = apic_set_affinity(data, mask, &dest);
-	if (ret)
-		return ret;
-
-	dmar_msi_read(irq, &msg);
-
-	msg.data &= ~MSI_DATA_VECTOR_MASK;
-	msg.data |= MSI_DATA_VECTOR(cfg->vector);
-	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
-	msg.address_lo |= MSI_ADDR_DEST_ID(dest);
-	msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
-
-	dmar_msi_write(irq, &msg);
+	ret = parent->chip->irq_set_affinity(parent, mask, force);
+	if (ret >= 0) {
+		dmar_msi_read(data->irq, &msg);
+		msi_update_msg(&msg, data);
+		dmar_msi_write(data->irq, &msg);
+	}
 
-	return IRQ_SET_MASK_OK_NOCOPY;
+	return ret;
 }
 
-static struct irq_chip dmar_msi_type = {
+static struct irq_chip dmar_msi_controller = {
 	.name			= "DMAR_MSI",
 	.irq_unmask		= dmar_msi_unmask,
 	.irq_mask		= dmar_msi_mask,
-	.irq_ack		= apic_ack_edge,
+	.irq_ack		= irq_chip_ack_parent,
 	.irq_set_affinity	= dmar_msi_set_affinity,
-	.irq_retrigger		= apic_retrigger_irq,
+	.irq_retrigger		= irq_chip_retrigger_hierarchy,
+	.irq_compose_msi_msg	= irq_msi_compose_msg,
 	.flags			= IRQCHIP_SKIP_SET_WAKE,
 };
 
-int dmar_alloc_hwirq(int id, int node, void *arg)
+static int dmar_domain_alloc(struct irq_domain *domain, unsigned int virq,
+			     unsigned int nr_irqs, void *arg)
+{
+	struct irq_alloc_info *info = arg;
+	int ret;
+
+	if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_DMAR)
+		return -EINVAL;
+	if (irq_find_mapping(domain, info->dmar_id)) {
+		pr_warn("IRQ for DMAR%d already exists.\n", info->dmar_id);
+		return -EEXIST;
+	}
+
+	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
+	if (ret >= 0) {
+		irq_domain_set_hwirq_and_chip(domain, virq, info->dmar_id,
+					      &dmar_msi_controller, NULL);
+		irq_set_handler_data(virq, info->dmar_data);
+		__irq_set_handler(virq, handle_edge_irq, 0, "edge");
+	}
+
+	return ret;
+}
+
+static void dmar_domain_free(struct irq_domain *domain, unsigned int virq,
+			     unsigned int nr_irqs)
+{
+	BUG_ON(nr_irqs > 1);
+	irq_domain_free_irqs_top(domain, virq, nr_irqs);
+}
+
+static void dmar_domain_activate(struct irq_domain *domain,
+				 struct irq_data *irq_data)
 {
-	int irq;
 	struct msi_msg msg;
 
-	irq = irq_domain_alloc_irqs(NULL, 1, node, NULL);
-	if (irq > 0) {
-		irq_set_handler_data(irq, arg);
-		irq_set_chip_and_handler_name(irq, &dmar_msi_type,
-					      handle_edge_irq, "edge");
-		native_compose_msi_msg(irq_cfg(irq), &msg);
-		dmar_msi_write(irq, &msg);
+	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
+	dmar_msi_write(irq_data->irq, &msg);
+}
+
+static void dmar_domain_deactivate(struct irq_domain *domain,
+				   struct irq_data *irq_data)
+{
+	struct msi_msg msg;
+
+	memset(&msg, 0, sizeof(msg));
+	dmar_msi_write(irq_data->irq, &msg);
+}
+
+static struct irq_domain_ops dmar_domain_ops = {
+	.alloc = dmar_domain_alloc,
+	.free = dmar_domain_free,
+	.activate = dmar_domain_activate,
+	.deactivate = dmar_domain_deactivate,
+};
+
+static struct irq_domain *dmar_get_irq_domain(void)
+{
+	static struct irq_domain *dmar_domain;
+	static DEFINE_MUTEX(dmar_lock);
+
+	mutex_lock(&dmar_lock);
+	if (dmar_domain == NULL) {
+		dmar_domain = irq_domain_add_tree(NULL, &dmar_domain_ops, NULL);
+		if (dmar_domain)
+			dmar_domain->parent = x86_vector_domain;
 	}
+	mutex_unlock(&dmar_lock);
+
+	return dmar_domain;
+}
+
+int dmar_alloc_hwirq(int id, int node, void *arg)
+{
+	struct irq_domain *domain = dmar_get_irq_domain();
+	struct irq_alloc_info info;
+
+	if (!domain)
+		return -1;
+
+	init_irq_alloc_info(&info, NULL);
+	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
+	info.dmar_id = id;
+	info.dmar_data = arg;
 
-	return irq;
+	return irq_domain_alloc_irqs(domain, 1, node, &info);
 }
 
 void dmar_free_hwirq(int irq)
 {
-	irq_set_handler_data(irq, NULL);
-	irq_set_handler(irq, NULL);
 	irq_domain_free_irqs(irq, 1);
 }
 #endif
-- 
1.7.10.4


  parent reply	other threads:[~2015-01-20  3:10 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-20  3:08 [Patch Part1 v7 00/38] Convert x86 to hierarchy irqdomain and stacked irqchip Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 01/38] x86/irq: Save destination CPU ID in irq_cfg Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 02/38] x86/irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 03/38] x86/hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 04/38] x86/MSI: " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 05/38] x86/uv: " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 06/38] x86/htirq: " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 07/38] x86/dmar: " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 08/38] irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 09/38] irq_remapping/vt-d: Change prototypes to prepare for enabling " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 10/38] irq_remapping/vt-d: Enhance Intel IR driver to suppport " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 11/38] irq_remapping/amd: Enhance AMD " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 12/38] x86/hpet: Enhance HPET IRQ to support " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 13/38] x86/MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 14/38] x86/irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 15/38] irq_remapping/vt-d: Clean up unused MSI related code Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 16/38] irq_remapping/amd: " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 17/38] irq_remapping: " Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 18/38] x86/MSI: Clean up unused MSI related code and interfaces Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 19/38] iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit Jiang Liu
2015-01-20  3:08 ` Jiang Liu [this message]
2015-01-20  3:08 ` [Patch Part1 v7 21/38] x86/htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 22/38] x86/uv: Use hierarchy irqdomain to manage UV interrupts Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 23/38] x86/irq: Normalize x86 irq_chip name Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 24/38] x86/MSI: Simplify the way to deal with remapped MSI interrupts Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 25/38] x86/MSI: Replace msi_update_msg() with irq_chip_compose_msi_msg() Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 26/38] x86/irq: Implement irq_chip.irq_write_msi_msg for MSI/DMAR/HPET irq_chips Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 27/38] x86/irq: Simplify MSI/DMAR/HPET implementation by using common code Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 28/38] irq_remapping: Kill unused function irq_remapping_print_chip() Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 29/38] x86/intel-mid: Delay initialization of APB timer Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 30/38] x86/intel-mid, trivial: Refine code syntax for sfi_parse_mtmr() Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 31/38] x86/apb_timer: Remove unused function is_apbt_capable() Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 32/38] x86/irq: Kill unused pre_init_apic_IRQ0() Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 33/38] x86/irq: Prepare IOAPIC interfaces to support hierarchy irqdomain Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 34/38] x86/irq: Implement callbacks to enable hierarchy irqdomain on IOAPICs Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 35/38] x86/irq: Refine the way to allocate irq_cfg for legacy IRQs Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 36/38] x86/irq: Simplify the way to print IOAPIC entry Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 37/38] x86/irq: Introduce helper functions to support hierarchy irqdomain for IOAPIC Jiang Liu
2015-01-20  3:08 ` [Patch Part1 v7 38/38] x86/irq: Convert IOAPIC to use hierarchy irqdomain interfaces Jiang Liu
2015-02-03  2:51 ` [Patch Part1 v7 00/38] Convert x86 to hierarchy irqdomain and stacked irqchip Jiang Liu

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