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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, "Rob Herring" <robh+dt@kernel.org>,
	"Eddie Huang" <eddie.huang@mediatek.com>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"Samuel Ortiz" <sameo@linux.intel.com>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Yingjoe Chen (陳英洲)" <Yingjoe.Chen@mediatek.com>,
	"Henry Chen" <henryc.chen@mediatek.com>,
	"YH Chen (陳昱豪)" <yh.chen@mediatek.com>,
	kernel@pengutronix.de, "Sascha Hauer" <s.hauer@pengutronix.de>
Subject: [PATCH 1/8] soc: Add MediaTek infracfg controller support
Date: Thu,  5 Feb 2015 16:25:31 +0100	[thread overview]
Message-ID: <1423149938-14471-2-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1423149938-14471-1-git-send-email-s.hauer@pengutronix.de>

This adds support for the MediaTek infracfg controller found
on the MT8135/MT8173 SoCs. The infracfg controller contains
miscellaneous registers for controlling peripheral resets and
clocks.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../devicetree/bindings/soc/mediatek/infracfg.txt  |  29 +++++
 drivers/soc/Kconfig                                |   1 +
 drivers/soc/Makefile                               |   1 +
 drivers/soc/mediatek/Kconfig                       |  12 ++
 drivers/soc/mediatek/Makefile                      |   1 +
 drivers/soc/mediatek/mtk-infracfg.c                | 127 +++++++++++++++++++++
 6 files changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/infracfg.txt
 create mode 100644 drivers/soc/mediatek/Kconfig
 create mode 100644 drivers/soc/mediatek/Makefile
 create mode 100644 drivers/soc/mediatek/mtk-infracfg.c

diff --git a/Documentation/devicetree/bindings/soc/mediatek/infracfg.txt b/Documentation/devicetree/bindings/soc/mediatek/infracfg.txt
new file mode 100644
index 0000000..1912b83
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/infracfg.txt
@@ -0,0 +1,29 @@
+MediaTek infracfg Controller
+============================
+
+The infracfg controller contains miscellaneous registers for controlling
+clocks, resets and bus settings.
+
+Required properties:
+- compatible: must be one of:
+	mediatek,mt8135-infracfg
+	mediatek,mt8173-infracfg
+- reg: Address range for the infracfg controller
+- #reset-cells: 1, see below
+
+Specifying reset lines connected to the infracfg controller
+===========================================================
+
+The infracfg controller provides various reset sources to other modules.
+Device nodes using these reset sources should specify the reset lines in
+a property containing a phandle to the infracfg node and a reset index.
+See include/dt-bindings/reset-controller/<soc>-resets.h for a list of valid
+indices.
+
+Example:
+
+	infracfg: infracfg@10001000 {
+		#reset-cells = <1>;
+		compatible = "mediatek,mt8135-infracfg";
+		reg = <0 0x10001000 0 0x1000>;
+	};
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 76d6bd4..d8bde82f0 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
 menu "SOC (System On Chip) specific Drivers"
 
+source "drivers/soc/mediatek/Kconfig"
 source "drivers/soc/qcom/Kconfig"
 source "drivers/soc/ti/Kconfig"
 source "drivers/soc/versatile/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..70042b2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the Linux Kernel SOC specific device drivers.
 #
 
+obj-$(CONFIG_ARCH_MEDIATEK)	+= mediatek/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_SOC_TI)		+= ti/
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
new file mode 100644
index 0000000..3ad39fe
--- /dev/null
+++ b/drivers/soc/mediatek/Kconfig
@@ -0,0 +1,12 @@
+#
+# MediaTek SoC drivers
+#
+config MTK_INFRACFG
+	tristate "MediaTek infracfg controller support"
+	depends on ARCH_MEDIATEK || COMPILE_TEST
+	select REGMAP
+	help
+	  The MediaTek infracfg controller found on MT8135 and MT8173 SoCs
+	  contains several miscellaneous registers for clock, reset and bus
+	  settings. Say yes here if you want to run your kernel on one of these
+	  SoCs.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
new file mode 100644
index 0000000..dbeb627
--- /dev/null
+++ b/drivers/soc/mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
new file mode 100644
index 0000000..3bbd39b
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-infracfg.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+struct mtk_infracfg {
+	struct regmap *regmap;
+	struct reset_controller_dev rcdev;
+};
+
+static int mtk_infracfg_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct mtk_infracfg *data = container_of(rcdev, struct mtk_infracfg, rcdev);
+
+	return regmap_update_bits(data->regmap, 0x30 + ((id / 32) << 2), BIT(id % 32), ~0u);
+}
+
+static int mtk_infracfg_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct mtk_infracfg *data = container_of(rcdev, struct mtk_infracfg, rcdev);
+
+	return regmap_update_bits(data->regmap, 0x30 + ((id / 32) << 2), BIT(id % 32), 0);
+}
+
+static int mtk_infracfg_reset(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	int ret;
+
+	ret = mtk_infracfg_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
+
+	return mtk_infracfg_reset_deassert(rcdev, id);
+}
+
+static struct reset_control_ops mtk_infracfg_reset_ops = {
+	.assert = mtk_infracfg_reset_assert,
+	.deassert = mtk_infracfg_reset_deassert,
+	.reset = mtk_infracfg_reset,
+};
+
+static struct regmap_config mtk_infracfg_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int mtk_infracfg_probe(struct platform_device *pdev)
+{
+	struct mtk_infracfg *data;
+	struct resource *res;
+	void __iomem *base;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	data->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+                                        &mtk_infracfg_regmap_config);
+	if (IS_ERR(data->regmap))
+		return PTR_ERR(data->regmap);
+
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.nr_resets = 64;
+	data->rcdev.ops = &mtk_infracfg_reset_ops;
+	data->rcdev.of_node = pdev->dev.of_node;
+
+	return reset_controller_register(&data->rcdev);
+}
+
+static int mtk_infracfg_remove(struct platform_device *pdev)
+{
+	struct mtk_infracfg *data = platform_get_drvdata(pdev);
+
+	reset_controller_unregister(&data->rcdev);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_infracfg_dt_ids[] = {
+	{
+		.compatible = "mediatek,mt8173-infracfg",
+	}, {
+		.compatible = "mediatek,mt8135-infracfg",
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, mtk_infracfg_dt_ids);
+
+static struct platform_driver mtk_infracfg_driver = {
+	.probe = mtk_infracfg_probe,
+	.remove = mtk_infracfg_remove,
+	.driver = {
+		.name = "mtk-infracfg",
+		.of_match_table = mtk_infracfg_dt_ids,
+	},
+};
+
+module_platform_driver(mtk_infracfg_driver);
+
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+MODULE_DESCRIPTION("MediaTek infracfg controller");
+MODULE_LICENSE("GPL");
-- 
2.1.4


  reply	other threads:[~2015-02-05 15:26 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-05 15:25 [PATCH v3] MediaTek PMIC support Sascha Hauer
2015-02-05 15:25 ` Sascha Hauer [this message]
2015-02-05 15:25 ` [PATCH 2/8] soc: Add MediaTek pericfg controller support Sascha Hauer
2015-02-05 15:25 ` [PATCH 3/8] dt: bindings: Add MediaTek MT8135/MT8173 reset controller defines Sascha Hauer
2015-02-05 15:25 ` [PATCH 4/8] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC Sascha Hauer
2015-02-05 15:25 ` [PATCH 5/8] ARM: dts: mt8135: Add pericfg, infracfg and pmic wrapper nodes Sascha Hauer
2015-02-05 15:25 ` [PATCH 6/8] ARM: dts: mt8135-evbp1: Add PMIC support Sascha Hauer
2015-02-05 15:25 ` [PATCH 7/8] mfd: dt-bindings: Add bindings for the MediaTek MT6397 PMIC Sascha Hauer
2015-02-05 15:25 ` [PATCH 8/8] mfd: Add support " Sascha Hauer
2015-02-05 17:05 ` [PATCH v3] MediaTek PMIC support Matthias Brugger
  -- strict thread matches above, loose matches on Subject: below --
2015-01-20  9:47 Sascha Hauer
2015-01-20  9:47 ` [PATCH 1/8] soc: Add MediaTek infracfg controller support Sascha Hauer
2015-01-20 16:14   ` Mark Rutland
2015-01-21  8:14     ` Sascha Hauer

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