From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752158AbbBVMDC (ORCPT ); Sun, 22 Feb 2015 07:03:02 -0500 Received: from metis.ext.pengutronix.de ([92.198.50.35]:49595 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752103AbbBVMC5 (ORCPT ); Sun, 22 Feb 2015 07:02:57 -0500 From: Sascha Hauer To: Matthias Brugger Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Eddie Huang , Yingjoe Chen , Henry Chen , YH Chen , kernel@pengutronix.de, linux-mediatek@lists.infradead.org, Sascha Hauer Subject: [PATCH 2/2] dt-bindings: ARM: Mediatek: document binding for the PMIC wrapper Date: Sun, 22 Feb 2015 13:02:47 +0100 Message-Id: <1424606567-29708-3-git-send-email-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1424606567-29708-1-git-send-email-s.hauer@pengutronix.de> References: <1424606567-29708-1-git-send-email-s.hauer@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds documentation for the PMIC wrapper unit found on Mediatek MT8135 and MT8173 SoCs. Signed-off-by: Sascha Hauer --- .../devicetree/bindings/soc/mediatek/pwrap.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/pwrap.txt diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt new file mode 100644 index 0000000..66cc528 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -0,0 +1,56 @@ +MediaTek PMIC Wrapper Driver + +This document describes the binding for the MediaTek PMIC wrapper. + +On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via +SPI. The SPI master interface is not directly visible to the CPU, but +only through the PMIC wrapper inside the SoC. The communication between +the SoC and the PMIC can optionally be encrypted. Also a non standard +Dual IO SPI mode can be used to increase speed. + +IP Pairing + +on MT8135 the pins of some SoC internal peripherals can be on the PMIC. +The signals of these pins are routed over the SPI bus using the pwrap +bridge. In the binding description below the properties needed for bridging +are marked with "IP Pairing". These are optional on SoCs which do not support +IP Pairing + +Required properties in pwrap device node. +- compatible: "mediatek,mt8135-pwrap" or "mediatek,mt8173-pwrap" +- interrupts: IRQ for pwrap in SOC +- reg-names: Must include the following entries: + "pwrap": Main registers base + "pwrap-bridge": bridge base (IP Pairing) +- reg: Must contain an entry for each entry in reg-names. +- reset-names: Must include the following entries: + "pwrap" + "pwrap-bridge" (IP Pairing) +- resets: Must contain an entry for each entry in reset-names. +- clock-names: Must include the following entries: + "spi": SPI bus clock + "wrap": Main module clock +- clocks: Must contain an entry for each entry in clock-names. + +Optional properities: +- pmic: Mediatek PMIC MFD is the child device of pwrap + See the following for child node definitions: + Documentation/devicetree/bindings/mfd/mt6397.txt + +Example: + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + + pmic { + compatible = "mediatek,mt6397"; + }; + }; -- 2.1.4