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From: Jisheng Zhang <jszhang@marvell.com>
To: <jg1.han@samsung.com>, <bhelgaas@google.com>,
	<Minghuan.Lian@freescale.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Jisheng Zhang <jszhang@marvell.com>
Subject: [PATCH 0/2] PCI: designware: improve iATU programming and usage
Date: Wed, 22 Apr 2015 20:58:12 +0800	[thread overview]
Message-ID: <1429707494-2732-1-git-send-email-jszhang@marvell.com> (raw)

The outbound iATU programming functions are similar, so PATCH1 consolidates
them into one.

Most transactions' type are cfg0 and MEM, so current iATU usage is not
balanced. PATCH2 adopts idea from Minghuan Lian <Minghuan.Lian@freescale.com>:

 http://www.spinics.net/lists/linux-pci/msg40440.html

to change the iATU allocation: iATU0 for cfg and IO, iATU1 for MEM.

Jisheng Zhang (2):
  PCI: designware: consolidate outbound iATU programming functions
  PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM

 drivers/pci/host/pcie-designware.c | 144 ++++++++++++++++---------------------
 1 file changed, 62 insertions(+), 82 deletions(-)

-- 
2.1.4


             reply	other threads:[~2015-04-22 13:01 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-22 12:58 Jisheng Zhang [this message]
2015-04-22 12:58 ` [PATCH 1/2] PCI: designware: consolidate outbound iATU programming functions Jisheng Zhang
2015-04-22 12:58 ` [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM Jisheng Zhang
2015-04-23  7:35   ` Fabrice Gasnier
2015-04-23  7:47     ` Jisheng Zhang

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