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* [PATCH 0/2] PCI: designware: improve iATU programming and usage
@ 2015-04-22 12:58 Jisheng Zhang
  2015-04-22 12:58 ` [PATCH 1/2] PCI: designware: consolidate outbound iATU programming functions Jisheng Zhang
  2015-04-22 12:58 ` [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM Jisheng Zhang
  0 siblings, 2 replies; 5+ messages in thread
From: Jisheng Zhang @ 2015-04-22 12:58 UTC (permalink / raw)
  To: jg1.han, bhelgaas, Minghuan.Lian
  Cc: linux-arm-kernel, linux-pci, linux-kernel, Jisheng Zhang

The outbound iATU programming functions are similar, so PATCH1 consolidates
them into one.

Most transactions' type are cfg0 and MEM, so current iATU usage is not
balanced. PATCH2 adopts idea from Minghuan Lian <Minghuan.Lian@freescale.com>:

 http://www.spinics.net/lists/linux-pci/msg40440.html

to change the iATU allocation: iATU0 for cfg and IO, iATU1 for MEM.

Jisheng Zhang (2):
  PCI: designware: consolidate outbound iATU programming functions
  PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM

 drivers/pci/host/pcie-designware.c | 144 ++++++++++++++++---------------------
 1 file changed, 62 insertions(+), 82 deletions(-)

-- 
2.1.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/2] PCI: designware: consolidate outbound iATU programming functions
  2015-04-22 12:58 [PATCH 0/2] PCI: designware: improve iATU programming and usage Jisheng Zhang
@ 2015-04-22 12:58 ` Jisheng Zhang
  2015-04-22 12:58 ` [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM Jisheng Zhang
  1 sibling, 0 replies; 5+ messages in thread
From: Jisheng Zhang @ 2015-04-22 12:58 UTC (permalink / raw)
  To: jg1.han, bhelgaas, Minghuan.Lian
  Cc: linux-arm-kernel, linux-pci, linux-kernel, Jisheng Zhang

Currently, the outbound iATU programming functions are similar, the only
difference is index, type, addr and size. This patch tries to consolidate
these functions into one. One side effect is it saves around 1700 bytes in
text:

   text	   data	    bss	    dec	    hex	filename
   9276	    204	      4	   9484	   250c pcie-designware.o-before
   7532	    204	      4	   7740	   1e3c pcie-designware.o

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pcie-designware.c | 109 +++++++++++++------------------------
 1 file changed, 39 insertions(+), 70 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 2e9f84f..1da1446 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -150,6 +150,21 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 	return ret;
 }
 
+static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
+		int type, u64 cpu_addr, u64 pci_addr, u32 size)
+{
+	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
+			  PCIE_ATU_VIEWPORT);
+	dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
+	dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
+	dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
+			  PCIE_ATU_LIMIT);
+	dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
+	dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+}
+
 static struct irq_chip dw_msi_irq_chip = {
 	.name = "PCI-MSI",
 	.irq_enable = pci_msi_unmask_irq,
@@ -515,68 +530,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	return 0;
 }
 
-static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
-{
-	/* Program viewport 0 : OUTBOUND : CFG0 */
-	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
-			  PCIE_ATU_VIEWPORT);
-	dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
-	dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
-	dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
-			  PCIE_ATU_LIMIT);
-	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
-	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
-	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
-static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
-{
-	/* Program viewport 1 : OUTBOUND : CFG1 */
-	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
-			  PCIE_ATU_VIEWPORT);
-	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
-	dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
-	dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
-			  PCIE_ATU_LIMIT);
-	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
-	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
-static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
-{
-	/* Program viewport 0 : OUTBOUND : MEM */
-	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
-			  PCIE_ATU_VIEWPORT);
-	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
-	dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
-	dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
-			  PCIE_ATU_LIMIT);
-	dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
-	dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
-			  PCIE_ATU_UPPER_TARGET);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
-static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
-{
-	/* Program viewport 1 : OUTBOUND : IO */
-	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
-			  PCIE_ATU_VIEWPORT);
-	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
-	dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
-	dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
-			  PCIE_ATU_LIMIT);
-	dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
-	dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
-			  PCIE_ATU_UPPER_TARGET);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 		u32 devfn, int where, int size, u32 *val)
 {
@@ -588,15 +541,23 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 	address = where & ~0x3;
 
 	if (bus->parent->number == pp->root_bus_nr) {
-		dw_pcie_prog_viewport_cfg0(pp, busdev);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+					  PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
+					  busdev, pp->cfg0_size);
 		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
 				val);
-		dw_pcie_prog_viewport_mem_outbound(pp);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+					  PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
+					  pp->mem_bus_addr, pp->mem_size);
 	} else {
-		dw_pcie_prog_viewport_cfg1(pp, busdev);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+					  PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
+					  busdev, pp->cfg1_size);
 		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
 				val);
-		dw_pcie_prog_viewport_io_outbound(pp);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+					  PCIE_ATU_TYPE_IO, pp->io_mod_base,
+					  pp->io_bus_addr, pp->io_size);
 	}
 
 	return ret;
@@ -613,15 +574,23 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 	address = where & ~0x3;
 
 	if (bus->parent->number == pp->root_bus_nr) {
-		dw_pcie_prog_viewport_cfg0(pp, busdev);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+					  PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
+					  busdev, pp->cfg0_size);
 		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
 				val);
-		dw_pcie_prog_viewport_mem_outbound(pp);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+					  PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
+					  pp->mem_bus_addr, pp->mem_size);
 	} else {
-		dw_pcie_prog_viewport_cfg1(pp, busdev);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+					  PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
+					  busdev, pp->cfg1_size);
 		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
 				val);
-		dw_pcie_prog_viewport_io_outbound(pp);
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+					  PCIE_ATU_TYPE_IO, pp->io_mod_base,
+					  pp->io_bus_addr, pp->io_size);
 	}
 
 	return ret;
-- 
2.1.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM
  2015-04-22 12:58 [PATCH 0/2] PCI: designware: improve iATU programming and usage Jisheng Zhang
  2015-04-22 12:58 ` [PATCH 1/2] PCI: designware: consolidate outbound iATU programming functions Jisheng Zhang
@ 2015-04-22 12:58 ` Jisheng Zhang
  2015-04-23  7:35   ` Fabrice Gasnier
  1 sibling, 1 reply; 5+ messages in thread
From: Jisheng Zhang @ 2015-04-22 12:58 UTC (permalink / raw)
  To: jg1.han, bhelgaas, Minghuan.Lian
  Cc: linux-arm-kernel, linux-pci, linux-kernel, Jisheng Zhang

Most transactions' type are cfg0 and MEM, so the Current iATU usage is not
balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors
the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation
ideas comes from Minghuan Lian <Minghuan.Lian@freescale.com>:

 http://www.spinics.net/lists/linux-pci/msg40440.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pcie-designware.c | 83 +++++++++++++++++++++-----------------
 1 file changed, 47 insertions(+), 36 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 1da1446..bb81c8ad 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -508,6 +508,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	if (pp->ops->host_init)
 		pp->ops->host_init(pp);
 
+	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+				  PCIE_ATU_TYPE_IO, pp->io_mod_base,
+				  pp->io_bus_addr, pp->io_size);
+	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+				  PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
+				  pp->mem_bus_addr, pp->mem_size);
+
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
 	/* program correct class for RC */
@@ -533,66 +540,70 @@ int dw_pcie_host_init(struct pcie_port *pp)
 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 		u32 devfn, int where, int size, u32 *val)
 {
-	int ret = PCIBIOS_SUCCESSFUL;
-	u32 address, busdev;
+	int ret, type;
+	u32 address, busdev, cfg_size;
+	u64 cpu_addr;
+	void __iomem *va_cfg_base;
 
 	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
 		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
 	address = where & ~0x3;
 
 	if (bus->parent->number == pp->root_bus_nr) {
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-					  PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
-					  busdev, pp->cfg0_size);
-		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
-				val);
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-					  PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
-					  pp->mem_bus_addr, pp->mem_size);
+		type = PCIE_ATU_TYPE_CFG0;
+		cpu_addr = pp->cfg0_mod_base;
+		cfg_size = pp->cfg0_size;
+		va_cfg_base = pp->va_cfg0_base;
 	} else {
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
-					  PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
-					  busdev, pp->cfg1_size);
-		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
-				val);
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
-					  PCIE_ATU_TYPE_IO, pp->io_mod_base,
-					  pp->io_bus_addr, pp->io_size);
+		type = PCIE_ATU_TYPE_CFG1;
+		cpu_addr = pp->cfg1_mod_base;
+		cfg_size = pp->cfg1_size;
+		va_cfg_base = pp->va_cfg1_base;
 	}
 
+	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+				  type, cpu_addr,
+				  busdev, cfg_size);
+	ret = dw_pcie_cfg_read(va_cfg_base + address, where, size, val);
+	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+				  PCIE_ATU_TYPE_IO, pp->io_mod_base,
+				  pp->io_bus_addr, pp->io_size);
+
 	return ret;
 }
 
 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 		u32 devfn, int where, int size, u32 val)
 {
-	int ret = PCIBIOS_SUCCESSFUL;
-	u32 address, busdev;
+	int ret, type;
+	u32 address, busdev, cfg_size;
+	u64 cpu_addr;
+	void __iomem *va_cfg_base;
 
 	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
 		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
 	address = where & ~0x3;
 
 	if (bus->parent->number == pp->root_bus_nr) {
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-					  PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
-					  busdev, pp->cfg0_size);
-		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
-				val);
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-					  PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
-					  pp->mem_bus_addr, pp->mem_size);
+		type = PCIE_ATU_TYPE_CFG0;
+		cpu_addr = pp->cfg0_mod_base;
+		cfg_size = pp->cfg0_size;
+		va_cfg_base = pp->va_cfg0_base;
 	} else {
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
-					  PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
-					  busdev, pp->cfg1_size);
-		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
-				val);
-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
-					  PCIE_ATU_TYPE_IO, pp->io_mod_base,
-					  pp->io_bus_addr, pp->io_size);
+		type = PCIE_ATU_TYPE_CFG1;
+		cpu_addr = pp->cfg1_mod_base;
+		cfg_size = pp->cfg1_size;
+		va_cfg_base = pp->va_cfg1_base;
 	}
 
+	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+				  type, cpu_addr,
+				  busdev, cfg_size);
+	ret = dw_pcie_cfg_write(va_cfg_base + address, where, size, val);
+	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+				  PCIE_ATU_TYPE_IO, pp->io_mod_base,
+				  pp->io_bus_addr, pp->io_size);
+
 	return ret;
 }
 
-- 
2.1.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM
  2015-04-22 12:58 ` [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM Jisheng Zhang
@ 2015-04-23  7:35   ` Fabrice Gasnier
  2015-04-23  7:47     ` Jisheng Zhang
  0 siblings, 1 reply; 5+ messages in thread
From: Fabrice Gasnier @ 2015-04-23  7:35 UTC (permalink / raw)
  To: Jisheng Zhang, jg1.han, bhelgaas, Minghuan.Lian
  Cc: linux-pci, linux-kernel, linux-arm-kernel

Hi Jisheng,

On 04/22/2015 02:58 PM, Jisheng Zhang wrote:
> Most transactions' type are cfg0 and MEM, so the Current iATU usage is not
> balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors
> the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation
> ideas comes from Minghuan Lian<Minghuan.Lian@freescale.com>:
>
>   http://www.spinics.net/lists/linux-pci/msg40440.html
>
> Signed-off-by: Jisheng Zhang<jszhang@marvell.com>
> ---
>   drivers/pci/host/pcie-designware.c | 83 +++++++++++++++++++++-----------------
>   1 file changed, 47 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 1da1446..bb81c8ad 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -508,6 +508,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
>   	if (pp->ops->host_init)
>   		pp->ops->host_init(pp);
>   
> +	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
> +				  PCIE_ATU_TYPE_IO, pp->io_mod_base,
> +				  pp->io_bus_addr, pp->io_size);
> +	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
> +				  PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
> +				  pp->mem_bus_addr, pp->mem_size);
> +
Some platforms doesn't have support for ATU. I think this is the reason 
to have
rd_other_conf / wr_other_conf ops in the driver.
IMO, this is not suitable to have this in the initialization routine for 
all platforms.

Regards,
Fabrice

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM
  2015-04-23  7:35   ` Fabrice Gasnier
@ 2015-04-23  7:47     ` Jisheng Zhang
  0 siblings, 0 replies; 5+ messages in thread
From: Jisheng Zhang @ 2015-04-23  7:47 UTC (permalink / raw)
  To: Fabrice Gasnier
  Cc: jg1.han, bhelgaas, Minghuan.Lian, linux-pci, linux-kernel,
	linux-arm-kernel

Hi Fabrice,

On Thu, 23 Apr 2015 00:35:10 -0700
Fabrice Gasnier <fabrice.gasnier@st.com> wrote:

> Hi Jisheng,
> 
> On 04/22/2015 02:58 PM, Jisheng Zhang wrote:
> > Most transactions' type are cfg0 and MEM, so the Current iATU usage is not
> > balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors
> > the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation
> > ideas comes from Minghuan Lian<Minghuan.Lian@freescale.com>:
> >
> >   http://www.spinics.net/lists/linux-pci/msg40440.html
> >
> > Signed-off-by: Jisheng Zhang<jszhang@marvell.com>
> > ---
> >   drivers/pci/host/pcie-designware.c | 83 +++++++++++++++++++++-----------------
> >   1 file changed, 47 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> > index 1da1446..bb81c8ad 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -508,6 +508,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
> >   	if (pp->ops->host_init)
> >   		pp->ops->host_init(pp);
> >   
> > +	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
> > +				  PCIE_ATU_TYPE_IO, pp->io_mod_base,
> > +				  pp->io_bus_addr, pp->io_size);
> > +	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
> > +				  PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
> > +				  pp->mem_bus_addr, pp->mem_size);
> > +
> Some platforms doesn't have support for ATU. I think this is the reason 
> to have
> rd_other_conf / wr_other_conf ops in the driver.

oops. Thanks for the information. So what about something like:

if (!pp->ops->rd_other_conf) {
	dw_pcie_prog_outbound_atu(...);
	dw_pcie_prog_outbound_atu(...);
}

Thanks,
Jisheng

> IMO, this is not suitable to have this in the initialization routine for 
> all platforms.
> 
> Regards,
> Fabrice


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2015-04-23  7:51 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-22 12:58 [PATCH 0/2] PCI: designware: improve iATU programming and usage Jisheng Zhang
2015-04-22 12:58 ` [PATCH 1/2] PCI: designware: consolidate outbound iATU programming functions Jisheng Zhang
2015-04-22 12:58 ` [PATCH 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM Jisheng Zhang
2015-04-23  7:35   ` Fabrice Gasnier
2015-04-23  7:47     ` Jisheng Zhang

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