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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Thomas Gleixner <tglx@linutronix.de>,
	"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Cc: "chenhc@lemote.com" <chenhc@lemote.com>,
	"paul.burton@mips.com" <paul.burton@mips.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"maz@kernel.org" <maz@kernel.org>
Subject: Re: [PATCH v1 1/2] genirq: Check for level based percpu irq
Date: Fri, 17 Jan 2020 10:23:45 +0800	[thread overview]
Message-ID: <1440861579227825@sas1-e05fd3bc78f9.qloud-c.yandex.net> (raw)
In-Reply-To: <875zhaeupr.fsf@nanos.tec.linutronix.de>



17.01.2020, 09:29, "Thomas Gleixner" <tglx@linutronix.de>:
> Jiaxun Yang <jiaxun.yang@flygoat.com> writes:
>>  MIPS processors implemented their IPI IRQ and CPU interrupt line
>>  as level triggered IRQ. However, our current percpu_irq flow is trying
>>  do it in a level triggered manner.
>

Hi Thomas,

Thanks for your kind explanation.

That appears to be my misunderstanding of the trigger type.

Paul, I have confirmed it seems fine to handle percpu IRQ without mask
it on both Ingenic and Loongson processors. How about other MIPS Cores?
Could you please help check that?

Thanks.

--
Jiaxun Yang

      reply	other threads:[~2020-01-17  2:23 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-13 10:12 [PATCH] irqchip: mips-cpu: Remove eoi operation Jiaxun Yang
2020-01-14 23:30 ` Paul Burton
2020-01-15  0:03   ` Jiaxun Yang
2020-01-15 13:40   ` Marc Zyngier
2020-01-15 14:23     ` Jiaxun Yang
2020-01-15 15:22       ` Marc Zyngier
2020-01-17  0:17 ` [PATCH v1 1/2] genirq: Check for level based percpu irq Jiaxun Yang
2020-01-17  0:17   ` [PATCH v1 2/2] irqchip: mips-cpu: Drop unnecessary ack/eoi operations Jiaxun Yang
2020-01-17  1:29   ` [PATCH v1 1/2] genirq: Check for level based percpu irq Thomas Gleixner
2020-01-17  2:23     ` Jiaxun Yang [this message]

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