From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752956AbeAZJfz (ORCPT ); Fri, 26 Jan 2018 04:35:55 -0500 Received: from mga07.intel.com ([134.134.136.100]:6945 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752649AbeAZJfu (ORCPT ); Fri, 26 Jan 2018 04:35:50 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,415,1511856000"; d="scan'208";a="22478846" Message-ID: <1516959345.7000.1281.camel@linux.intel.com> Subject: Re: [PATCH v2 2/3] gpiolib-of: Support 'reserved-gpio-ranges' property From: Andy Shevchenko To: Stephen Boyd , Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Timur Tabi , Bjorn Andersson , linux-gpio@vger.kernel.org, Grant Likely , devicetree@vger.kernel.org Date: Fri, 26 Jan 2018 11:35:45 +0200 In-Reply-To: <20180126011400.2191-3-sboyd@codeaurora.org> References: <20180126011400.2191-1-sboyd@codeaurora.org> <20180126011400.2191-3-sboyd@codeaurora.org> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2018-01-25 at 17:13 -0800, Stephen Boyd wrote: > Some qcom platforms make some GPIOs or pins unavailable for use > by non-secure operating systems, and thus reading or writing the > registers for those pins will cause access control issues. Add > support for a DT property to describe the set of GPIOs that are > available for use so that higher level OSes are able to know what > pins to avoid reading/writing. > > For now, we plumb this into the gpiochip irq APIs so that > GPIO/pinctrl drivers can use the gpiochip_irqchip_irq_valid() to > test validity of GPIOs. > +static void of_gpiochip_init_irq_valid_mask(struct gpio_chip *chip) > +{ > + int len, i; > + u32 start, count; > + struct device_node *np = chip->of_node; Perhaps reversed tree style? (In the following function as well) > + len = of_property_count_u32_elems(np, "reserved-gpio- > ranges"); > > + for (i = 0; i < len; i += 2) { > + of_property_read_u32_index(np, "reserved-gpio- > ranges", > + i, &start); > + of_property_read_u32_index(np, "reserved-gpio- > ranges", > + i + 1, &count); of_find_property() + of_prop_next_u32() ? > + if (size > 0 && size % 2 == 0) > + gpiochip->irq.need_valid_mask = true; ffs(size) >= 2 ? -- Andy Shevchenko Intel Finland Oy