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From: Stephen Boyd <sboyd@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	afaerber@suse.de, mark.rutland@arm.com, mturquette@baylibre.com,
	robh+dt@kernel.org
Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com,
	96boards@ucrobotics.com, devicetree@vger.kernel.org,
	davem@davemloft.net, mchehab@kernel.org,
	daniel.thompson@linaro.org, amit.kucheria@linaro.org,
	viresh.kumar@linaro.org, hzhang@ucrobotics.com,
	bdong@ucrobotics.com, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	manivannanece23@gmail.com,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: Re: [PATCH v5 05/12] clk: actions: Add gate clock support
Date: Mon, 19 Mar 2018 18:04:25 -0700	[thread overview]
Message-ID: <152150786513.254778.147481994658886771@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20180317100952.28538-6-manivannan.sadhasivam@linaro.org>

Quoting Manivannan Sadhasivam (2018-03-17 03:09:45)
> diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c
> new file mode 100644
> index 000000000000..25dd94ac0f35
> --- /dev/null
> +++ b/drivers/clk/actions/owl-gate.c
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// OWL gate clock driver
> +//
> +// Copyright (c) 2014 Actions Semi Inc.
> +// Author: David Liu <liuwei@actions-semi.com>
> +//
> +// Copyright (c) 2018 Linaro Ltd.
> +// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +
> +#include "owl-gate.h"
> +
> +void clk_gate_set(const struct owl_clk_common *common,

owl_gate_set?

> +                const struct owl_gate_hw *gate_hw, bool enable)
> +{
> +       int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
> +       u32 reg;
> +
> +       set ^= enable;
> +
> +       regmap_read(common->regmap, gate_hw->reg, &reg);
> +
> +       if (set)
> +               reg |= BIT(gate_hw->bit_idx);
> +       else
> +               reg &= ~BIT(gate_hw->bit_idx);
> +
> +       regmap_write(common->regmap, gate_hw->reg, reg);
> +}
> +
> +static void owl_gate_disable(struct clk_hw *hw)
> +{
> +       struct owl_gate *gate = hw_to_owl_gate(hw);
> +       struct owl_clk_common *common = &gate->common;
> +
> +       clk_gate_set(common, &gate->gate_hw, false);
> +}
> +
> +static int owl_gate_enable(struct clk_hw *hw)
> +{
> +       struct owl_gate *gate = hw_to_owl_gate(hw);
> +       struct owl_clk_common *common = &gate->common;
> +
> +       clk_gate_set(common, &gate->gate_hw, true);
> +
> +       return 0;
> +}
> +
> +int clk_is_enabled(const struct owl_clk_common *common,

Can this be called owl_gate_is_enabled?

> +                  const struct owl_gate_hw *gate_hw)
> +{
> +       u32 reg;
> +
> +       regmap_read(common->regmap, gate_hw->reg, &reg);
> +
> +       if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
> +               reg ^= BIT(gate_hw->bit_idx);
> +
> +       return !!(reg & BIT(gate_hw->bit_idx));
> +}
> +
> +static int owl_gate_is_enabled(struct clk_hw *hw)
> +{
> +       struct owl_gate *gate = hw_to_owl_gate(hw);
> +       struct owl_clk_common *common = &gate->common;
> +
> +       return clk_is_enabled(common, &gate->gate_hw);
> +}
> +
> +const struct clk_ops owl_gate_ops = {

Everything going to be builtin? If anything is a module then this needs
to be exported.

> +       .disable        = owl_gate_disable,
> +       .enable         = owl_gate_enable,
> +       .is_enabled     = owl_gate_is_enabled,
> +};

Otherwise looks good.

  reply	other threads:[~2018-03-20  1:04 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-17 10:09 [PATCH v5 00/12] Add clock driver for Actions S900 SoC Manivannan Sadhasivam
2018-03-17 10:09 ` [PATCH v5 01/12] dt-bindings: clock: Add Actions S900 clock bindings Manivannan Sadhasivam
2018-03-20  0:59   ` Stephen Boyd
2018-03-17 10:09 ` [PATCH v5 02/12] arm64: dts: actions: Add S900 clock management unit nodes Manivannan Sadhasivam
2018-03-17 10:09 ` [PATCH v5 03/12] arm64: dts: actions: Source CMU clock for UART5 Manivannan Sadhasivam
2018-03-17 10:09 ` [PATCH v5 04/12] clk: actions: Add common clock driver support Manivannan Sadhasivam
2018-03-20  1:02   ` Stephen Boyd
2018-03-17 10:09 ` [PATCH v5 05/12] clk: actions: Add gate clock support Manivannan Sadhasivam
2018-03-20  1:04   ` Stephen Boyd [this message]
2018-03-17 10:09 ` [PATCH v5 06/12] clk: actions: Add mux " Manivannan Sadhasivam
2018-03-20  1:05   ` Stephen Boyd
2018-03-17 10:09 ` [PATCH v5 07/12] clk: actions: Add divider " Manivannan Sadhasivam
2018-03-20  1:06   ` Stephen Boyd
2018-03-17 10:09 ` [PATCH v5 08/12] clk: actions: Add factor " Manivannan Sadhasivam
2018-03-18 20:31   ` kbuild test robot
2018-03-20  1:08   ` Stephen Boyd
2018-03-20  1:11   ` Stephen Boyd
2018-03-20  1:41   ` kbuild test robot
2018-03-17 10:09 ` [PATCH v5 09/12] clk: actions: Add fixed " Manivannan Sadhasivam
2018-03-20  1:10   ` Stephen Boyd
2018-03-20  9:04     ` Manivannan Sadhasivam
2018-03-20 17:15       ` Stephen Boyd
2018-03-17 10:09 ` [PATCH v5 10/12] clk: actions: Add composite " Manivannan Sadhasivam
2018-03-17 10:09 ` [PATCH v5 11/12] clk: actions: Add pll " Manivannan Sadhasivam
2018-03-17 10:09 ` [PATCH v5 12/12] clk: actions: Add S900 SoC " Manivannan Sadhasivam
2018-03-18 20:38   ` kbuild test robot
2018-03-18 21:28   ` kbuild test robot
2018-03-20  7:16   ` Stephen Boyd

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