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From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com,
	linux-kernel@vger.kernel.org, joro@8bytes.org,
	Chao Peng <chao.p.peng@linux.intel.com>,
	Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v6 02/11] perf/x86/intel/pt: Change pt_cap_get() to a public function
Date: Tue, 20 Mar 2018 19:21:49 +0800	[thread overview]
Message-ID: <1521544918-31084-3-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1521544918-31084-1-git-send-email-luwei.kang@intel.com>

From: Chao Peng <chao.p.peng@linux.intel.com>

Change pt_cap_get() to a public function so that KVM can access it.
Introduce new capablility PT_CAP_output_subsys to support
of output to Trace Transport subsystem.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 arch/x86/events/intel/pt.c      |  4 +++-
 arch/x86/events/intel/pt.h      | 21 ---------------------
 arch/x86/include/asm/intel_pt.h | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 22 deletions(-)

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 6d6dd4f..d89dd8c 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -68,6 +68,7 @@
 	PT_CAP(topa_output,		0, CPUID_ECX, BIT(0)),
 	PT_CAP(topa_multiple_entries,	0, CPUID_ECX, BIT(1)),
 	PT_CAP(single_range_output,	0, CPUID_ECX, BIT(2)),
+	PT_CAP(output_subsys,		0, CPUID_ECX, BIT(3)),
 	PT_CAP(payloads_lip,		0, CPUID_ECX, BIT(31)),
 	PT_CAP(num_address_ranges,	1, CPUID_EAX, 0x3),
 	PT_CAP(mtc_periods,		1, CPUID_EAX, 0xffff0000),
@@ -75,7 +76,7 @@
 	PT_CAP(psb_periods,		1, CPUID_EBX, 0xffff0000),
 };
 
-static u32 pt_cap_get(enum pt_capabilities cap)
+u32 pt_cap_get(enum pt_capabilities cap)
 {
 	struct pt_cap_desc *cd = &pt_caps[cap];
 	u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
@@ -83,6 +84,7 @@ static u32 pt_cap_get(enum pt_capabilities cap)
 
 	return (c & cd->mask) >> shift;
 }
+EXPORT_SYMBOL_GPL(pt_cap_get);
 
 static ssize_t pt_cap_show(struct device *cdev,
 			   struct device_attribute *attr,
diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h
index 0050ca1..269e15a 100644
--- a/arch/x86/events/intel/pt.h
+++ b/arch/x86/events/intel/pt.h
@@ -45,30 +45,9 @@ struct topa_entry {
 	u64	rsvd4	: 16;
 };
 
-#define PT_CPUID_LEAVES		2
-#define PT_CPUID_REGS_NUM	4 /* number of regsters (eax, ebx, ecx, edx) */
-
 /* TSC to Core Crystal Clock Ratio */
 #define CPUID_TSC_LEAF		0x15
 
-enum pt_capabilities {
-	PT_CAP_max_subleaf = 0,
-	PT_CAP_cr3_filtering,
-	PT_CAP_psb_cyc,
-	PT_CAP_ip_filtering,
-	PT_CAP_mtc,
-	PT_CAP_ptwrite,
-	PT_CAP_power_event_trace,
-	PT_CAP_topa_output,
-	PT_CAP_topa_multiple_entries,
-	PT_CAP_single_range_output,
-	PT_CAP_payloads_lip,
-	PT_CAP_num_address_ranges,
-	PT_CAP_mtc_periods,
-	PT_CAP_cycle_thresholds,
-	PT_CAP_psb_periods,
-};
-
 struct pt_pmu {
 	struct pmu		pmu;
 	u32			caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index b523f51..2de4db0 100644
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -2,10 +2,34 @@
 #ifndef _ASM_X86_INTEL_PT_H
 #define _ASM_X86_INTEL_PT_H
 
+#define PT_CPUID_LEAVES		2
+#define PT_CPUID_REGS_NUM	4 /* number of regsters (eax, ebx, ecx, edx) */
+
+enum pt_capabilities {
+	PT_CAP_max_subleaf = 0,
+	PT_CAP_cr3_filtering,
+	PT_CAP_psb_cyc,
+	PT_CAP_ip_filtering,
+	PT_CAP_mtc,
+	PT_CAP_ptwrite,
+	PT_CAP_power_event_trace,
+	PT_CAP_topa_output,
+	PT_CAP_topa_multiple_entries,
+	PT_CAP_single_range_output,
+	PT_CAP_output_subsys,
+	PT_CAP_payloads_lip,
+	PT_CAP_num_address_ranges,
+	PT_CAP_mtc_periods,
+	PT_CAP_cycle_thresholds,
+	PT_CAP_psb_periods,
+};
+
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
 void cpu_emergency_stop_pt(void);
+extern u32 pt_cap_get(enum pt_capabilities cap);
 #else
 static inline void cpu_emergency_stop_pt(void) {}
+static inline u32 pt_cap_get(enum pt_capabilities cap) { return 0; }
 #endif
 
 #endif /* _ASM_X86_INTEL_PT_H */
-- 
1.8.3.1

  parent reply	other threads:[~2018-03-21  1:11 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-20 11:21 [PATCH v6 00/11] Intel Processor Trace virtualization enabling Luwei Kang
2018-03-20 11:21 ` [PATCH v6 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2018-04-30 13:57   ` Peter Zijlstra
2018-05-02  7:41     ` Kang, Luwei
2018-03-20 11:21 ` Luwei Kang [this message]
2018-04-30 13:59   ` [PATCH v6 02/11] perf/x86/intel/pt: Change pt_cap_get() to a public function Peter Zijlstra
2018-03-20 11:21 ` [PATCH v6 03/11] perf/x86/intel/pt: Introduce a new function to get the capability of Intel PT Luwei Kang
2018-04-30 14:01   ` Peter Zijlstra
2018-03-20 11:21 ` [PATCH v6 04/11] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2018-03-20 11:21 ` [PATCH v6 05/11] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-03-20 11:21 ` [PATCH v6 06/11] KVM: x86: Add Intel processor trace context for each vcpu Luwei Kang
2018-03-20 11:21 ` [PATCH v6 07/11] KVM: x86: Implement Intel Processor Trace context switch Luwei Kang
2018-03-20 11:21 ` [PATCH v6 08/11] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-03-20 11:21 ` [PATCH v6 09/11] KVM: x86: Implement Intel Processor Trace MSRs read/write Luwei Kang
2018-03-20 11:21 ` [PATCH v6 10/11] KVM: x86: Set intercept for Intel PT MSRs Luwei Kang
2018-03-20 11:21 ` [PATCH v6 11/11] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-04-30 13:17 ` [PATCH v6 00/11] Intel Processor Trace virtualization enabling Paolo Bonzini

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