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From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com,
	linux-kernel@vger.kernel.org, joro@8bytes.org,
	Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v6 08/11] KVM: x86: Introduce a function to initialize the PT configuration
Date: Tue, 20 Mar 2018 19:21:55 +0800	[thread overview]
Message-ID: <1521544918-31084-9-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1521544918-31084-1-git-send-email-luwei.kang@intel.com>

Initialize the Intel PT configuration when cpuid update.
Include cpuid inforamtion, rtit_ctl bit mask and the number of
address ranges.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 arch/x86/kvm/vmx.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 34bcb30..5166d72 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -10191,6 +10191,71 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
 #undef cr4_fixed1_update
 }
 
+static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
+{
+	struct vcpu_vmx *vmx = to_vmx(vcpu);
+	struct kvm_cpuid_entry2 *best = NULL;
+	int i;
+
+	for (i = 0; i < PT_CPUID_LEAVES; i++) {
+		best = kvm_find_cpuid_entry(vcpu, 0x14, i);
+		if (!best)
+			return;
+		vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
+		vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
+		vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
+		vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
+	}
+
+	/* Get the number of configurable Address Ranges for filtering */
+	vmx->pt_desc.range_cnt = __pt_cap_get(vmx->pt_desc.caps,
+						PT_CAP_num_address_ranges);
+
+	/* Clear the no dependency bits */
+	vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
+			RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DIS_RETC);
+
+	/* If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set */
+	if (__pt_cap_get(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
+		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3_FILTER;
+
+	/*
+	 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
+	 * PSBFreq can be set
+	 */
+	if (__pt_cap_get(vmx->pt_desc.caps, PT_CAP_psb_cyc))
+		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYC_EN |
+			RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
+
+	/*
+	 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
+	 * MTCFreq can be set
+	 */
+	if (__pt_cap_get(vmx->pt_desc.caps, PT_CAP_mtc))
+		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
+			RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
+
+	/* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
+	if (__pt_cap_get(vmx->pt_desc.caps, PT_CAP_ptwrite))
+		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
+						RTIT_CTL_PTW_EN);
+
+	/* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
+	if (__pt_cap_get(vmx->pt_desc.caps, PT_CAP_power_event_trace))
+		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
+
+	/* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
+	if (__pt_cap_get(vmx->pt_desc.caps, PT_CAP_topa_output))
+		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
+	/* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
+	if (__pt_cap_get(vmx->pt_desc.caps, PT_CAP_output_subsys))
+		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
+
+	/* unmask address range configure area */
+	for (i = 0; i < vmx->pt_desc.range_cnt; i++)
+		vmx->pt_desc.ctl_bitmask &= ~(0xf << (32 + i*4));
+}
+
 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
@@ -10209,6 +10274,10 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
 
 	if (nested_vmx_allowed(vcpu))
 		nested_vmx_cr_fixed1_bits_update(vcpu);
+
+	if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
+		guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
+		update_intel_pt_cfg(vcpu);
 }
 
 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
-- 
1.8.3.1

  parent reply	other threads:[~2018-03-21  1:13 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-20 11:21 [PATCH v6 00/11] Intel Processor Trace virtualization enabling Luwei Kang
2018-03-20 11:21 ` [PATCH v6 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2018-04-30 13:57   ` Peter Zijlstra
2018-05-02  7:41     ` Kang, Luwei
2018-03-20 11:21 ` [PATCH v6 02/11] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2018-04-30 13:59   ` Peter Zijlstra
2018-03-20 11:21 ` [PATCH v6 03/11] perf/x86/intel/pt: Introduce a new function to get the capability of Intel PT Luwei Kang
2018-04-30 14:01   ` Peter Zijlstra
2018-03-20 11:21 ` [PATCH v6 04/11] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2018-03-20 11:21 ` [PATCH v6 05/11] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-03-20 11:21 ` [PATCH v6 06/11] KVM: x86: Add Intel processor trace context for each vcpu Luwei Kang
2018-03-20 11:21 ` [PATCH v6 07/11] KVM: x86: Implement Intel Processor Trace context switch Luwei Kang
2018-03-20 11:21 ` Luwei Kang [this message]
2018-03-20 11:21 ` [PATCH v6 09/11] KVM: x86: Implement Intel Processor Trace MSRs read/write Luwei Kang
2018-03-20 11:21 ` [PATCH v6 10/11] KVM: x86: Set intercept for Intel PT MSRs Luwei Kang
2018-03-20 11:21 ` [PATCH v6 11/11] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-04-30 13:17 ` [PATCH v6 00/11] Intel Processor Trace virtualization enabling Paolo Bonzini

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