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From: Sinan Kaya <okaya@codeaurora.org>
To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org
Cc: linux-arm-msm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Sinan Kaya <okaya@codeaurora.org>,
	linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 3/5] io: define stronger ordering for the default writeX() implementation
Date: Thu,  5 Apr 2018 09:09:11 -0400	[thread overview]
Message-ID: <1522933753-19589-3-git-send-email-okaya@codeaurora.org> (raw)
In-Reply-To: <1522933753-19589-1-git-send-email-okaya@codeaurora.org>

The default implementation of mapping writeX() to __raw_writeX() is wrong.
writeX() has stronger ordering semantics. Compiler is allowed to reorder
memory writes against __raw_writeX().

Use the previously defined __io_aw() and __io_bw() macros to harden
code generation according to architecture support.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
 include/asm-generic/io.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index d27e8af..964725e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -208,7 +208,9 @@ static inline u64 readq(const volatile void __iomem *addr)
 #define writeb writeb
 static inline void writeb(u8 value, volatile void __iomem *addr)
 {
+	__io_bw();
 	__raw_writeb(value, addr);
+	__io_aw();
 }
 #endif
 
@@ -216,7 +218,9 @@ static inline void writeb(u8 value, volatile void __iomem *addr)
 #define writew writew
 static inline void writew(u16 value, volatile void __iomem *addr)
 {
+	__io_bw();
 	__raw_writew(cpu_to_le16(value), addr);
+	__io_aw();
 }
 #endif
 
@@ -224,7 +228,9 @@ static inline void writew(u16 value, volatile void __iomem *addr)
 #define writel writel
 static inline void writel(u32 value, volatile void __iomem *addr)
 {
+	__io_bw();
 	__raw_writel(__cpu_to_le32(value), addr);
+	__io_aw();
 }
 #endif
 
@@ -233,7 +239,9 @@ static inline void writel(u32 value, volatile void __iomem *addr)
 #define writeq writeq
 static inline void writeq(u64 value, volatile void __iomem *addr)
 {
+	__io_bw();
 	__raw_writeq(__cpu_to_le64(value), addr);
+	__io_aw();
 }
 #endif
 #endif /* CONFIG_64BIT */
-- 
2.7.4

  parent reply	other threads:[~2018-04-05 13:10 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-05 13:09 [PATCH v4 1/5] io: define several IO & PIO barrier types for the asm-generic version Sinan Kaya
2018-04-05 13:09 ` [PATCH v4 2/5] io: define stronger ordering for the default readX() implementation Sinan Kaya
2018-04-05 13:09 ` Sinan Kaya [this message]
2018-04-05 13:09 ` [PATCH v4 4/5] io: change outX() to have their own IO barrier overrides Sinan Kaya
2018-04-05 13:09 ` [PATCH v4 5/5] io: change inX() " Sinan Kaya
2018-04-06 10:19 ` [PATCH v4 1/5] io: define several IO & PIO barrier types for the asm-generic version Arnd Bergmann
2018-04-06 12:50   ` okaya
2018-04-06 13:20     ` Arnd Bergmann

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