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From: Stephen Boyd <sboyd@kernel.org>
To: Doug Anderson <dianders@chromium.org>,
	Manu Gautam <mgautam@codeaurora.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Rob Herring <robh@kernel.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	LKML <linux-kernel@vger.kernel.org>,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Vivek Gautam <vivek.gautam@codeaurora.org>,
	Evan Green <evgreen@chromium.org>,
	linux-arm-msm@vger.kernel.org, Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	"open list:ARM/QUALCOMM SUPPORT" <linux-soc@vger.kernel.org>,
	"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 1/7] clk: msm8996-gcc: change halt check for USB/PCIE pipe_clk
Date: Thu, 05 Apr 2018 13:07:19 -0700	[thread overview]
Message-ID: <152295883900.91052.4792431636170417291@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <CAD=FV=UXvf+_rvbFGrHAQ1N0kbrMR_c2=LBVD=AMuL6DAjWO+Q@mail.gmail.com>

Quoting Doug Anderson (2018-03-29 13:55:55)
> Hi,
> 
> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam <mgautam@codeaurora.org> wrote:
> > The USB and PCIE pipe clocks are sourced from external clocks
> > inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
> > clocks is dependent on PHY initialization sequence hence
> > update halt_check to BRANCH_HALT_DELAY for these clocks so
> > that clock status bit is not polled when enabling or disabling
> > the clocks. It allows to simplify PHY client driver code which
> > is both user and source of the pipe_clk and avoid error logging
> > related status check on clk_disable/enable.
> >
> > Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
> > ---
> >  drivers/clk/qcom/gcc-msm8996.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> 
> As per my feedback on <https://patchwork.kernel.org/patch/10314937/>,
> I'm not a fan of this.  Hopefully we can adjust the PHY driver so it's
> not needed.
> 

Agreed. We should be able to enable the clks at the right time and halt
bits should work. From what I can recall we had that working before on
db820c, so has something changed?

  reply	other threads:[~2018-04-05 20:07 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-29 11:04 [PATCH v4 0/7] phy: qcom: Updates for USB PHYs on SDM845 Manu Gautam
2018-03-29 11:04 ` [PATCH v4 1/7] clk: msm8996-gcc: change halt check for USB/PCIE pipe_clk Manu Gautam
2018-03-29 20:55   ` Doug Anderson
2018-04-05 20:07     ` Stephen Boyd [this message]
2018-04-10  6:44       ` Manu Gautam
2018-03-29 11:04 ` [PATCH v4 2/7] phy: qcom-qmp: Enable pipe_clk before PHY initialization Manu Gautam
2018-03-29 17:28   ` Evan Green
2018-03-29 18:44   ` Doug Anderson
2018-03-29 20:54     ` Doug Anderson
2018-04-10  6:36       ` Manu Gautam
2018-04-10 15:05         ` Doug Anderson
2018-04-10 18:32           ` Stephen Boyd
2018-04-11 15:37             ` Manu Gautam
2018-04-12 20:38               ` Stephen Boyd
2018-04-13  7:00                 ` Manu Gautam
2018-03-29 11:04 ` [PATCH v4 3/7] phy: qcom-qusb2: Fix crash if nvmem cell not specified Manu Gautam
2018-03-29 11:04 ` [PATCH v4 4/7] dt-bindings: phy-qcom-qmp: Update bindings for sdm845 Manu Gautam
2018-03-29 19:39   ` Doug Anderson
2018-03-29 11:04 ` [PATCH v4 5/7] phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support " Manu Gautam
2018-03-29 11:04 ` [PATCH v4 6/7] dt-bindings: phy-qcom-usb2: Add support to override tuning values Manu Gautam
2018-03-29 20:38   ` Doug Anderson
2018-04-09 20:18     ` Rob Herring
2018-04-10  7:16       ` Manu Gautam
2018-04-12 20:47         ` Doug Anderson
2018-04-16  1:36           ` Manu Gautam
2018-03-29 11:04 ` [PATCH v4 7/7] phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845 Manu Gautam
2018-03-29 20:38   ` Doug Anderson
2018-04-10  6:55     ` Manu Gautam

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