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From: Sinan Kaya <okaya@codeaurora.org>
To: linux-parisc@vger.kernel.org, arnd@arndb.de,
	timur@codeaurora.org, sulrich@codeaurora.org
Cc: linux-arm-msm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Sinan Kaya <okaya@codeaurora.org>,
	"James E.J. Bottomley" <jejb@parisc-linux.org>,
	Helge Deller <deller@gmx.de>,
	Thomas Gleixner <tglx@linutronix.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Philippe Ombredanne <pombredanne@nexb.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 1/2] parisc: define stronger ordering for the default writeX()
Date: Tue, 17 Apr 2018 00:08:50 -0400	[thread overview]
Message-ID: <1523938133-3224-1-git-send-email-okaya@codeaurora.org> (raw)

parisc architecture seems to be mapping writeX() and writeX_relaxed() APIs
to __raw_writeX() API.

__raw_writeX() API doesn't provide any kind of ordering guarantees.
commit 755bd04aaf4b ("io: define stronger ordering for the default writeX()
implementation") changed asm-generic implementation to use a more
conservative approach towards the writeX() API.

Place a barrier() before the register write so that compiler doesn't
optimize across the regiter operation.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
 arch/parisc/include/asm/io.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h
index afe493b..2ec6405 100644
--- a/arch/parisc/include/asm/io.h
+++ b/arch/parisc/include/asm/io.h
@@ -196,18 +196,22 @@ static inline unsigned long long readq(const volatile void __iomem *addr)
 
 static inline void writeb(unsigned char b, volatile void __iomem *addr)
 {
+	barrier();
 	__raw_writeb(b, addr);
 }
 static inline void writew(unsigned short w, volatile void __iomem *addr)
 {
+	barrier();
 	__raw_writew((__u16 __force) cpu_to_le16(w), addr);
 }
 static inline void writel(unsigned int l, volatile void __iomem *addr)
 {
+	barrier();
 	__raw_writel((__u32 __force) cpu_to_le32(l), addr);
 }
 static inline void writeq(unsigned long long q, volatile void __iomem *addr)
 {
+	barrier();
 	__raw_writeq((__u64 __force) cpu_to_le64(q), addr);
 }
 
-- 
2.7.4

             reply	other threads:[~2018-04-17  4:08 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-17  4:08 Sinan Kaya [this message]
2018-04-17  4:08 ` [PATCH v2 2/2] parisc: define stronger ordering for the default readX() Sinan Kaya
2018-04-17  9:37   ` James Bottomley
2018-04-17 14:13     ` Sinan Kaya
2018-04-17 15:55       ` James Bottomley
2018-04-17 18:28         ` Sinan Kaya
2018-04-17 22:53           ` John David Anglin
2018-04-18 13:39             ` Sinan Kaya

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