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* [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c
@ 2018-04-30  7:11 Ludovic Barre
  2018-04-30  7:11 ` [PATCH 1/2] " Ludovic Barre
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Ludovic Barre @ 2018-04-30  7:11 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland
  Cc: Maxime Coquelin, Alexandre Torgue, devicetree, linux-arm-kernel,
	linux-kernel, Ludovic Barre

From: Ludovic Barre <ludovic.barre@st.com>

This patch series adds qspi support for stm32mp157c SoC
and its eval board.

Ludovic Barre (2):
  ARM: dts: stm32: add qspi support for stm32mp157c
  ARM: dts: stm32: add flash nor support on stm32mp157c eval board

 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 45 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stm32mp157c-ev1.dts     | 25 +++++++++++++++++
 arch/arm/boot/dts/stm32mp157c.dtsi        | 11 ++++++++
 3 files changed, 81 insertions(+)

-- 
2.7.4

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 1/2] ARM: dts: stm32: add qspi support for stm32mp157c
  2018-04-30  7:11 [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c Ludovic Barre
@ 2018-04-30  7:11 ` Ludovic Barre
  2018-04-30  7:11 ` [PATCH 2/2] ARM: dts: stm32: add flash nor support on stm32mp157c eval board Ludovic Barre
  2018-05-03 13:06 ` [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c Alexandre Torgue
  2 siblings, 0 replies; 4+ messages in thread
From: Ludovic Barre @ 2018-04-30  7:11 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland
  Cc: Maxime Coquelin, Alexandre Torgue, devicetree, linux-arm-kernel,
	linux-kernel, Ludovic Barre

From: Ludovic Barre <ludovic.barre@st.com>

This patch adds qspi support on stm32mp157c,
read in memory mapped, write in indirect mode.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index bfcf84b..7714949 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/reset/stm32mp1-resets.h>
 
 / {
 	#address-cells = <1>;
@@ -167,6 +168,16 @@
 			#reset-cells = <1>;
 		};
 
+		qspi: qspi@58003000 {
+			compatible = "st,stm32f469-qspi";
+			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+			reg-names = "qspi", "qspi_mm";
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc QSPI_K>;
+			resets = <&rcc QSPI_R>;
+			status = "disabled";
+		};
+
 		usart1: serial@5c000000 {
 			compatible = "st,stm32h7-uart";
 			reg = <0x5c000000 0x400>;
-- 
2.7.4

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 2/2] ARM: dts: stm32: add flash nor support on stm32mp157c eval board
  2018-04-30  7:11 [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c Ludovic Barre
  2018-04-30  7:11 ` [PATCH 1/2] " Ludovic Barre
@ 2018-04-30  7:11 ` Ludovic Barre
  2018-05-03 13:06 ` [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c Alexandre Torgue
  2 siblings, 0 replies; 4+ messages in thread
From: Ludovic Barre @ 2018-04-30  7:11 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland
  Cc: Maxime Coquelin, Alexandre Torgue, devicetree, linux-arm-kernel,
	linux-kernel, Ludovic Barre

From: Ludovic Barre <ludovic.barre@st.com>

This patch adds flash nor on qspi. Each flash is
connected in quad mode and has its own chip select.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 45 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stm32mp157c-ev1.dts     | 25 +++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 6f044100..9d4c553 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -146,6 +146,51 @@
 				gpio-ranges = <&pinctrl 0 160 8>;
 			};
 
+			qspi_clk_pins_a: qspi-clk-0 {
+				pins {
+					pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <3>;
+				};
+			};
+
+			qspi_bk1_pins_a: qspi-bk1-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+						 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
+						 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
+						 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <3>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+					bias-pull-up;
+					drive-push-pull;
+					slew-rate = <3>;
+				};
+			};
+
+			qspi_bk2_pins_a: qspi-bk2-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
+						 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
+						 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
+						 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <3>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
+					bias-pull-up;
+					drive-push-pull;
+					slew-rate = <3>;
+				};
+			};
+
 			uart4_pins_a: uart4@0 {
 				pins1 {
 					pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 57e6dbc..96c2aee 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -19,3 +19,28 @@
 		serial0 = &uart4;
 	};
 };
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash0: mx66l51235l@0 {
+		reg = <0>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <108000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	flash1: mx66l51235l@1 {
+		reg = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <108000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
-- 
2.7.4

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c
  2018-04-30  7:11 [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c Ludovic Barre
  2018-04-30  7:11 ` [PATCH 1/2] " Ludovic Barre
  2018-04-30  7:11 ` [PATCH 2/2] ARM: dts: stm32: add flash nor support on stm32mp157c eval board Ludovic Barre
@ 2018-05-03 13:06 ` Alexandre Torgue
  2 siblings, 0 replies; 4+ messages in thread
From: Alexandre Torgue @ 2018-05-03 13:06 UTC (permalink / raw)
  To: Ludovic Barre, Rob Herring, Mark Rutland
  Cc: Maxime Coquelin, devicetree, linux-arm-kernel, linux-kernel

Hi Ludovic,

On 04/30/2018 09:11 AM, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
> 
> This patch series adds qspi support for stm32mp157c SoC
> and its eval board.
> 
> Ludovic Barre (2):
>    ARM: dts: stm32: add qspi support for stm32mp157c
>    ARM: dts: stm32: add flash nor support on stm32mp157c eval board
> 
>   arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 45 +++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/stm32mp157c-ev1.dts     | 25 +++++++++++++++++
>   arch/arm/boot/dts/stm32mp157c.dtsi        | 11 ++++++++
>   3 files changed, 81 insertions(+)
> 

Series applied on stm32-next.

Regards
Alex

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2018-05-03 13:07 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2018-04-30  7:11 [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c Ludovic Barre
2018-04-30  7:11 ` [PATCH 1/2] " Ludovic Barre
2018-04-30  7:11 ` [PATCH 2/2] ARM: dts: stm32: add flash nor support on stm32mp157c eval board Ludovic Barre
2018-05-03 13:06 ` [PATCH 0/2] ARM: dts: stm32: add qspi support for stm32mp157c Alexandre Torgue

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