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From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Taniya Das <tdas@codeaurora.org>
Cc: Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Rajendra Nayak <rnayak@codeaurora.org>,
	Odelu Kukatla <okukatla@codeaurora.org>,
	Amit Nischal <anischal@codeaurora.org>,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Taniya Das <tdas@codeaurora.org>
Subject: Re: [PATCH 2/2] clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
Date: Wed, 02 May 2018 08:27:08 -0700	[thread overview]
Message-ID: <152527482828.138124.7114901348273696817@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1525258277-3478-3-git-send-email-tdas@codeaurora.org>

Quoting Taniya Das (2018-05-02 03:51:17)
> +
> +static DEFINE_MUTEX(rpmh_clk_lock);
> +
> +#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,   \
> +                         _res_en_offset, _res_on)                      \
> +       static struct clk_rpmh _platform##_##_name_active;              \
> +       static struct clk_rpmh _platform##_##_name = {                  \
> +               .res_name = _res_name,                                  \
> +               .res_addr = _res_en_offset,                             \
> +               .res_on_val = _res_on,                                  \
> +               .peer = &_platform##_##_name_active,                    \
> +               .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |        \
> +                                     BIT(RPMH_ACTIVE_ONLY_STATE) |     \
> +                                     BIT(RPMH_SLEEP_STATE)),           \
> +               .hw.init = &(struct clk_init_data){                     \
> +                       .ops = &clk_rpmh_ops,                           \
> +                       .name = #_name,                                 \
> +                       .parent_names = (const char *[]){ "xo_board",   \
> +                                               "xo_board_div" },       \

The rpmh clks that do a div 2 can have a recalc_rate function that
returns the xo_board clk rate divided by 2 all the time. That may be
easier to do. Keep xo_board as parent, but then specify if it does div-2
or div-1 in the SoC specific listing. Then DT can only show 38.4 MHz.
The div 2 part is inside the SoC anyway so this seems more accurate too.

> +                       .num_parents = 2,                               \
> +               },                                                      \
> +       };                                                              \

  reply	other threads:[~2018-05-02 15:27 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-02 10:51 [v6 0/2] " Taniya Das
2018-05-02 10:51 ` [PATCH 1/2] dt-bindings: clock: Introduce QCOM RPMh clock bindings Taniya Das
2018-05-02 15:10   ` Stephen Boyd
2018-05-02 10:51 ` [PATCH 2/2] clk: qcom: clk-rpmh: Add QCOM RPMh clock driver Taniya Das
2018-05-02 15:27   ` Stephen Boyd [this message]
2018-05-02 15:30   ` Stephen Boyd
2018-05-03 10:33     ` Taniya Das
2018-05-03 17:04       ` Stephen Boyd
2018-05-02 15:12 ` [v6 0/2] " Stephen Boyd

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