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From: Ilia Lin <ilialin@codeaurora.org>
To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
	mark.rutland@arm.com, rjw@rjwysocki.net, viresh.kumar@linaro.org,
	lgirdwood@gmail.com, broonie@kernel.org, andy.gross@linaro.org,
	david.brown@linaro.org, catalin.marinas@arm.com,
	will.deacon@arm.com, linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	rnayak@codeaurora.org, ilialin@codeaurora.org,
	amit.kucheria@linaro.org, nicolas.dechesne@linaro.org,
	celster@codeaurora.org, tfinkel@codeaurora.org
Subject: [PATCH v5 04/14] clk: qcom: Add DT bindings for CPU clock driver for msm8996
Date: Thu,  3 May 2018 14:52:25 +0300	[thread overview]
Message-ID: <1525348355-25471-5-git-send-email-ilialin@codeaurora.org> (raw)
In-Reply-To: <1525348355-25471-1-git-send-email-ilialin@codeaurora.org>

Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below

                             +-------+
              XO             |       |
          +------------------>0      |
                             |       |
                   PLL/2     | SMUX  +----+
                     +------->1      |    |
                     |       |       |    |
                     |       +-------+    |    +-------+
                     |                    +---->0      |
                     |                         |       |
+---------------+    |             +----------->1      | CPU clk
|Primary PLL    +----+ PLL_EARLY   |           |       +------>
|               +------+-----------+    +------>2 PMUX |
+---------------+      |                |      |       |
                       |   +------+     |   +-->3      |
                       +--^+  ACD +-----+   |  +-------+
+---------------+          +------+         |
|Alt PLL        |                           |
|               +---------------------------+
+---------------+         PLL_EARLY

The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.

The primary PLL operates on a single VCO range, between 600MHz
and 3GHz. However the CPUs do support OPPs with frequencies
between 300MHz and 600MHz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.

Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/clock/qcom,kryocc.txt | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,kryocc.txt b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt
new file mode 100644
index 0000000..8458783
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt
@@ -0,0 +1,17 @@
+Qualcomm CPUSS clock controller for Kryo CPUs
+----------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+			"qcom,msm8996-apcc"
+
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+
+Example:
+	kryocc: clock-controller@6400000 {
+		compatible = "qcom,msm8996-apcc";
+		reg = <0x6400000 0x90000>;
+		#clock-cells = <1>;
+	};
-- 
1.9.1

  parent reply	other threads:[~2018-05-03 11:53 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-03 11:52 [PATCH v5 00/14] CPU scaling support " Ilia Lin
2018-05-03 11:52 ` [PATCH v5 01/14] soc: qcom: Separate kryo l2 accessors from PMU driver Ilia Lin
2018-05-03 11:52 ` [PATCH v5 02/14] clk: qcom: Make clk_alpha_pll_configure available to modules Ilia Lin
2018-05-03 11:52 ` [PATCH v5 03/14] clk: qcom: Add CPU clock driver for msm8996 Ilia Lin
2018-05-04 12:27   ` kbuild test robot
2018-05-03 11:52 ` Ilia Lin [this message]
2018-05-03 11:52 ` [PATCH v5 05/14] clk: qcom: cpu-8996: Add support to switch to alternate PLL Ilia Lin
2018-05-03 11:52 ` [PATCH v5 06/14] clk: qcom: cpu-8996: Add support to switch below 600Mhz Ilia Lin
2018-05-03 11:52 ` [PATCH v5 07/14] clk: qcom: Add ACD path to CPU clock driver for msm8996 Ilia Lin
2018-05-03 11:52 ` [PATCH v5 08/14] dt: qcom: Add opp and thermal to the msm8996 Ilia Lin
2018-05-03 11:52 ` [PATCH v5 09/14] regulator: qcom_spmi: Add support for SAW Ilia Lin
2018-05-03 11:52 ` [PATCH v5 10/14] dt-bindings: qcom_spmi: Add support for SAW documentation Ilia Lin
2018-05-07 16:07   ` Rob Herring
2018-05-03 11:52 ` [PATCH v5 11/14] dt: qcom: Add SAW regulator for 8x96 CPUs Ilia Lin
2018-05-03 11:52 ` [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driver Ilia Lin
2018-05-04  6:08   ` Viresh Kumar
2018-05-04  6:44     ` ilialin
2018-05-04  6:57       ` Viresh Kumar
2018-05-04 19:20         ` ilialin
2018-05-03 11:52 ` [PATCH v5 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu Ilia Lin
2018-05-04  6:11   ` Viresh Kumar
2018-05-04  6:46     ` ilialin
2018-05-03 11:52 ` [PATCH v5 14/14] dt: qcom: Add qcom-cpufreq-kryo driver configuration Ilia Lin
2018-05-04  6:00 ` [PATCH v5 00/14] CPU scaling support for msm8996 Viresh Kumar

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