[PATCH v1 1/2] dt-bindings: clock: Introduce QCOM Video clock controller bindings

[Amit Nischal <anischal@codeaurora.org>]

Add device tree bindings for video clock controller for Qualcomm
Technology Inc's SoCs.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,videocc.txt     | 18 ++++++++++++++++
 include/dt-bindings/clock/qcom,videocc-sdm845.h    | 25 ++++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt
 create mode 100644 include/dt-bindings/clock/qcom,videocc-sdm845.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
new file mode 100644
index 0000000..600eda2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
@@ -0,0 +1,18 @@
+Qualcomm Video Clock & Reset Controller Binding
+-----------------------------------------------
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-videocc"
+- reg : shall contain base register location and length
+- #clock-cells : from common clock binding, shall contain 1.
+- #reset-cells : from common reset binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Example:
+	videocc: clock-controller@ab00000 {
+		compatible = "qcom,sdm845-videocc";
+		reg = <0xab00000 0x10000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		#power-domain-cells = <1>;
+	};
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 0000000..48f6a9e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+#ifndef _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
+#define _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
+
+#define VIDEO_CC_APB_CLK			0
+#define VIDEO_CC_AT_CLK				1
+#define VIDEO_CC_QDSS_TRIG_CLK			2
+#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK		3
+#define VIDEO_CC_VCODEC0_AXI_CLK		4
+#define VIDEO_CC_VCODEC0_CORE_CLK		5
+#define VIDEO_CC_VCODEC1_AXI_CLK		6
+#define VIDEO_CC_VCODEC1_CORE_CLK		7
+#define VIDEO_CC_VENUS_AHB_CLK			8
+#define VIDEO_CC_VENUS_CLK_SRC			9
+#define VIDEO_CC_VENUS_CTL_AXI_CLK		10
+#define VIDEO_CC_VENUS_CTL_CORE_CLK		11
+#define VIDEO_PLL0				12
+
+#define VENUS_GDSC				0
+#define VCODEC0_GDSC				1
+#define VCODEC1_GDSC				2
+
+#endif
--
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