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From: Stephen Boyd <>
To: Alexandre Belloni <>,
	Boris Brezillon <>,
	Greg Kroah-Hartman <>,
	Marcin Ziemianowicz <>,
	Nicolas Ferre <>
Cc: Marcin Ziemianowicz <>,,
	Boris Brezillon <>,
	Michael Turquette <>,,,
Subject: Re: [PATCH V4] clk: at91: PLL recalc_rate() now using cached MUL and DIV values
Date: Tue, 15 May 2018 23:39:42 -0700	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Quoting Marcin Ziemianowicz (2018-04-29 12:01:11)
> When a USB device is connected to the USB host port on the SAM9N12 then
> you get "-62" error which seems to indicate USB replies from the device
> are timing out. Based on a logic sniffer, I saw the USB bus was running
> at half speed.
> The PLL code uses cached MUL and DIV values which get set in set_rate()
> and applied in prepare(), but the recalc_rate() function instead
> queries the hardware instead of using these cached values. Therefore,
> if recalc_rate() is called between a set_rate() and prepare(), the
> wrong frequency is calculated and later the USB clock divider for the
> SAM9N12 SOC will be configured for an incorrect clock.
> In my case, the PLL hardware was set to 96 Mhz before the OHCI
> driver loads, and therefore the usb clock divider was being set
> to /2 even though the OHCI driver set the PLL to 48 Mhz.
> As an alternative explanation, I noticed this was fixed in the past by
> 87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL
> driver") but the bug was later re-introduced by 1bdf02326b71 ("clk:
> at91: make use of syscon/regmap internally").
> Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally)
> Cc: <>
> Signed-off-by: Marcin Ziemianowicz <>
> ---

Applied to clk-next

      parent reply	other threads:[~2018-05-16  6:39 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-29 19:01 Marcin Ziemianowicz
2018-04-30  5:58 ` Boris Brezillon
2018-05-09  4:32   ` Marcin Ziemianowicz
2018-05-15 23:04     ` Stephen Boyd
2018-05-16  6:39 ` Stephen Boyd [this message]

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