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From: Stephen Boyd <swboyd@chromium.org>
To: rishabhb@codeaurora.org
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm@lists.infradead.org, tsoni@codeaurora.org,
	ckadabi@codeaurora.org, evgreen@chromium.org, robh@kernel.org
Subject: Re: [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
Date: Wed, 16 May 2018 11:08:57 -0700	[thread overview]
Message-ID: <152649413707.210890.2655572242392552759@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <385198cbb91c4a36ad758997916ad271@codeaurora.org>

Quoting rishabhb@codeaurora.org (2018-05-16 10:33:14)
> On 2018-05-16 10:03, Stephen Boyd wrote:
> > Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
> 
> >> +
> >> +- max-slices:
> >> +       usage: required
> >> +       Value Type: <u32>
> >> +       Definition: Number of cache slices supported by hardware
> >> +
> >> +Example:
> >> +
> >> +       llcc: qcom,llcc@1100000 {
> > 
> > cache-controller@1100000 ?
> > 
> We have tried to use consistent naming convention as in llcc_* 
> everywhere.
> Using cache-controller will mix and match the naming convention. Also in
> the documentation it is explained what llcc is and its full form.
> 

DT prefers standard node names as opposed to vendor specific node names.
Isn't it a cache controller? I fail to see why this can't be done.

  reply	other threads:[~2018-05-16 18:09 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-08 20:21 [PATCH v6 0/2] SDM845 System Cache Driver Rishabh Bhatnagar
2018-05-08 20:22 ` [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc Rishabh Bhatnagar
2018-05-16 17:03   ` Stephen Boyd
2018-05-16 17:33     ` rishabhb
2018-05-16 18:08       ` Stephen Boyd [this message]
2018-05-16 23:32         ` rishabhb
2018-05-18 14:31           ` Rob Herring
2018-05-08 20:22 ` [PATCH v6 2/2] drivers: soc: Add LLCC driver Rishabh Bhatnagar
2018-05-10 20:15   ` Evan Green

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