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From: Michel Pollet <michel.pollet@bp.renesas.com>
To: linux-renesas-soc@vger.kernel.org, Simon Horman <horms@verge.net.au>
Cc: phil.edworthy@renesas.com,
	Michel Pollet <buserror+upstream@gmail.com>,
	Michel Pollet <michel.pollet@bp.renesas.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v7 2/5] dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
Date: Thu, 24 May 2018 10:28:40 +0100	[thread overview]
Message-ID: <1527154169-32380-3-git-send-email-michel.pollet@bp.renesas.com> (raw)
In-Reply-To: <1527154169-32380-1-git-send-email-michel.pollet@bp.renesas.com>

The Renesas R9A06G032 SYSCTRL node description.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 .../bindings/clock/renesas,r9a06g032-sysctrl.txt   | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt

diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
new file mode 100644
index 0000000..63eb66cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
@@ -0,0 +1,32 @@
+* Renesas R9A06G032 SYSCTRL
+
+Required Properties:
+
+  - compatible: Must be:
+    - "renesas,r9a06g032-sysctrl"
+  - reg: Base address and length of the SYSCTRL IO block.
+  - #clock-cells: Must be 1
+
+Examples
+--------
+
+  - SYSCTRL node:
+
+	sysctrl: sysctrl@4000c000 {
+		compatible = "renesas,r9a06g032-sysctrl";
+		reg = <0x4000c000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+  - Other nodes can use the clocks provided by SYSCTRL as in:
+
+	#include <dt-bindings/clock/r9a06g032-sysctrl.h>
+	uart0: serial@40060000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x40060000 0x400>;
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		clocks = <&sysctrl R9A06G032_CLK_UART0>;
+		clock-names = "baudclk";
+	};
-- 
2.7.4

  parent reply	other threads:[~2018-05-24  9:34 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-24  9:28 [PATCH v7 0/5] arm: Base support for Renesas RZN1D-DB Board Michel Pollet
2018-05-24  9:28 ` [PATCH v7 1/5] dt-bindings: Add the r9a06g032-sysctrl.h file Michel Pollet
2018-05-25 10:31   ` Geert Uytterhoeven
2018-05-31  9:11     ` M P
2018-05-31  9:32       ` Geert Uytterhoeven
2018-05-31 10:01         ` M P
2018-06-01  8:18           ` Geert Uytterhoeven
2018-05-24  9:28 ` Michel Pollet [this message]
2018-05-25  9:23   ` [PATCH v7 2/5] dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation Geert Uytterhoeven
2018-05-31 10:16     ` M P
2018-06-01  8:22       ` Geert Uytterhoeven
2018-05-24  9:28 ` [PATCH v7 3/5] ARM: dts: Renesas R9A06G032 base device tree file Michel Pollet
2018-05-25  9:27   ` Geert Uytterhoeven
2018-05-28  9:15     ` Simon Horman
2018-05-24  9:28 ` [PATCH v7 4/5] ARM: dts: Renesas RZN1D-DB Board base file Michel Pollet
2018-05-25  9:28   ` Geert Uytterhoeven
2018-05-24  9:28 ` [PATCH v7 5/5] clk: renesas: Renesas R9A06G032 clock driver Michel Pollet
2018-05-26 13:45   ` kbuild test robot
2018-05-30 19:49   ` Geert Uytterhoeven

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