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From: Stephen Boyd <swboyd@chromium.org>
To: Doug Anderson <dianders@chromium.org>
Cc: Andy Gross <andy.gross@linaro.org>,
	Evan Green <evgreen@chromium.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Rob Herring <robh@kernel.org>,
	devicetree@vger.kernel.org, cang@codeaurora.org,
	LKML <linux-kernel@vger.kernel.org>,
	Manu Gautam <mgautam@codeaurora.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v5 1/5] dt-bindings: phy-qcom-qmp: Fix register underspecification
Date: Fri, 09 Nov 2018 16:53:18 -0800	[thread overview]
Message-ID: <154181119838.88331.10401425771645606506@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <CAD=FV=UKfDsthT4W3H4jR0Qvw-izLShCjWngN2uBrY-FUEtDDQ@mail.gmail.com>

Quoting Doug Anderson (2018-11-05 08:52:39)
> On Sat, Nov 3, 2018 at 7:40 PM Stephen Boyd <swboyd@chromium.org> wrote:
> > > +                       clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
> > > +                       clock-names = "pipe0";
> > > +                       clock-output-names = "usb3_uni_phy_pipe_clk_src";
> >
> > If this has clock-output-names then I would expect to see a #clock-cells
> > property, but that isn't here in this node. Are we relying on the same
> > property in the parent node?
> 
> If I had to guess, I believe it's yet more confusing than that.  I
> believe you actually point to the parent phandle if you want to use
> the clock.  I notice that the parent has #clock-cells as 1 so
> presumably this is how you point to one child or the other?  ...but I
> don't think it's documented how this works.

There are 'clock-ranges', that almost nobody uses. It might be usable
for this purpose.

> The lane nodes don't have
> any sort of ID as far as I can tell.  ...and in any case having
> #clock-cells of 1 makes no sense for USB 3 PHYs which are supposed to
> only have one child?
> 
> Let's look at the code, maybe?  Hrm, phy_pipe_clk_register() takes no
> ID or anything.  Huh?  OK, so as far as I can tell
> of_clk_add_provider() is never called on this clock...
> 
> So I think the answer is that #clock-cells should be <0> and should
> move to the child node to match with clock-output-names.  Then I guess
> (if anyone references this clock from the device tree rather than
> relying on the global clock-output-names) we should add the
> of_clk_add_provider() into the code?
> 
> Maybe we can add that as a patch to the end of this series?  There are
> so many crazy / random things wrong with these bindings that it makes
> sense to make smaller / incremental changes?
> 

Sure that sounds fine. It would be another case where a driver would
want to call the proposed devm_of_clk_add_parent_provider() API.


  reply	other threads:[~2018-11-10  0:53 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-26 17:35 [PATCH v5 0/5] arm64: dts: qcom: sdm845: Add UFS DT nodes Evan Green
2018-10-26 17:35 ` [PATCH v5 1/5] dt-bindings: phy-qcom-qmp: Fix register underspecification Evan Green
2018-11-04  2:40   ` Stephen Boyd
2018-11-05 16:52     ` Doug Anderson
2018-11-10  0:53       ` Stephen Boyd [this message]
2018-10-26 17:35 ` [PATCH v5 2/5] phy: qcom-qmp: Utilize fully-specified DT registers Evan Green
2018-10-26 17:35 ` [PATCH v5 3/5] arm64: dts: qcom: sdm845: add UFS controller Evan Green
2018-11-22  7:18   ` Bjorn Andersson
2018-11-28 23:43     ` Evan Green
2018-10-26 17:35 ` [PATCH v5 4/5] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Evan Green
2018-11-19 19:19   ` Stephen Boyd
2018-11-19 19:25     ` Doug Anderson
2018-11-19 19:42       ` Stephen Boyd
2018-11-22  7:04         ` Bjorn Andersson
2018-11-28  2:31           ` Stephen Boyd
2018-10-26 17:35 ` [PATCH v5 5/5] arm64: dts: qcom: sdm845: Add USB PHY lane two Evan Green
2018-11-22  7:07   ` Bjorn Andersson

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