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From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<ldewangan@nvidia.com>, <broonie@kernel.org>
Cc: <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>,
	Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: [PATCH V5 1/4] spi: tegra114: add support for gpio based CS
Date: Mon, 13 May 2019 22:03:52 -0700	[thread overview]
Message-ID: <1557810235-16401-2-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1557810235-16401-1-git-send-email-skomatineni@nvidia.com>

This patch adds support for GPIO based CS control through SPI core
function spi_set_cs.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index b1f31bb16659..f47417dd9edb 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -776,6 +776,10 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 		} else
 			tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 
+		/* GPIO based chip select control */
+		if (spi->cs_gpiod)
+			gpiod_set_value(spi->cs_gpiod, 1);
+
 		command1 |= SPI_CS_SW_HW;
 		if (spi->mode & SPI_CS_HIGH)
 			command1 |= SPI_CS_SW_VAL;
@@ -864,6 +868,10 @@ static int tegra_spi_setup(struct spi_device *spi)
 	}
 
 	spin_lock_irqsave(&tspi->lock, flags);
+	/* GPIO based chip select control */
+	if (spi->cs_gpiod)
+		gpiod_set_value(spi->cs_gpiod, 0);
+
 	val = tspi->def_command1_reg;
 	if (spi->mode & SPI_CS_HIGH)
 		val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
@@ -893,6 +901,10 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 	int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
 
+	/* GPIO based chip select control */
+	if (spi->cs_gpiod)
+		gpiod_set_value(spi->cs_gpiod, 0);
+
 	if (cs_val)
 		tspi->command1_reg |= SPI_CS_SW_VAL;
 	else
@@ -1199,6 +1211,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
 		master->max_speed_hz = 25000000; /* 25MHz */
 
 	/* the spi->mode bits understood by this driver: */
+	master->use_gpio_descriptors = true;
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
 			    SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
-- 
2.7.4


  reply	other threads:[~2019-05-14  5:04 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-14  5:03 [PATCH V5 0/4] additional features to Tegra SPI Sowjanya Komatineni
2019-05-14  5:03 ` Sowjanya Komatineni [this message]
2019-05-14  9:33   ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Jon Hunter
2019-05-14 17:18     ` Sowjanya Komatineni
2019-05-14 17:31       ` Jon Hunter
2019-05-15  9:35       ` Mark Brown
2019-05-15 11:24         ` Sowjanya Komatineni
2019-05-15 11:29           ` Mark Brown
     [not found]             ` <BYAPR12MB3398528B86D3DE9CC3AA6D85C2090@BYAPR12MB3398.namprd12.prod.outlook.com>
2019-05-15 11:42               ` Mark Brown
2019-05-15 11:18   ` Applied "spi: tegra114: add support for gpio based CS" to the spi tree Mark Brown
2019-05-14  5:03 ` [PATCH V5 2/4] spi: tegra114: add support for hw based cs Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for hw based cs" to the spi tree Mark Brown
2019-05-14  5:03 ` [PATCH V5 3/4] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for HW CS timing" to the spi tree Mark Brown
2019-05-14  5:03 ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for TX and RX trimmers" to the spi tree Mark Brown
2019-05-23  1:02   ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Nathan Chancellor
2019-05-23  1:10     ` Sowjanya Komatineni

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