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From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<ldewangan@nvidia.com>, <broonie@kernel.org>
Cc: <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>,
	Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: [PATCH V5 2/4] spi: tegra114: add support for hw based cs
Date: Mon, 13 May 2019 22:03:53 -0700	[thread overview]
Message-ID: <1557810235-16401-3-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1557810235-16401-1-git-send-email-skomatineni@nvidia.com>

Tegra SPI controller supports both HW and SW based CS control
for SPI transfers.

This patch adds support for HW based CS control where CS is driven
to active state during the transfer and is driven inactive at the
end of the transfer directly by the HW.

This patch enables the use of HW based CS only for single transfers
without cs_change request.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 39 +++++++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index f47417dd9edb..0cb0932d32fd 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -193,6 +193,7 @@ struct tegra_spi_data {
 	unsigned				dma_buf_size;
 	unsigned				max_buf_size;
 	bool					is_curr_dma_xfer;
+	bool					use_hw_based_cs;
 
 	struct completion			rx_dma_complete;
 	struct completion			tx_dma_complete;
@@ -723,7 +724,9 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 }
 
 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
-		struct spi_transfer *t, bool is_first_of_msg)
+					struct spi_transfer *t,
+					bool is_first_of_msg,
+					bool is_single_xfer)
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 	u32 speed = t->speed_hz;
@@ -780,11 +783,17 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 		if (spi->cs_gpiod)
 			gpiod_set_value(spi->cs_gpiod, 1);
 
-		command1 |= SPI_CS_SW_HW;
-		if (spi->mode & SPI_CS_HIGH)
-			command1 |= SPI_CS_SW_VAL;
-		else
-			command1 &= ~SPI_CS_SW_VAL;
+		if (is_single_xfer && !(t->cs_change)) {
+			tspi->use_hw_based_cs = true;
+			command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
+		} else {
+			tspi->use_hw_based_cs = false;
+			command1 |= SPI_CS_SW_HW;
+			if (spi->mode & SPI_CS_HIGH)
+				command1 |= SPI_CS_SW_VAL;
+			else
+				command1 &= ~SPI_CS_SW_VAL;
+		}
 
 		tegra_spi_writel(tspi, 0, SPI_COMMAND2);
 	} else {
@@ -905,11 +914,14 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
 	if (spi->cs_gpiod)
 		gpiod_set_value(spi->cs_gpiod, 0);
 
-	if (cs_val)
-		tspi->command1_reg |= SPI_CS_SW_VAL;
-	else
-		tspi->command1_reg &= ~SPI_CS_SW_VAL;
-	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	if (!tspi->use_hw_based_cs) {
+		if (cs_val)
+			tspi->command1_reg |= SPI_CS_SW_VAL;
+		else
+			tspi->command1_reg &= ~SPI_CS_SW_VAL;
+		tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	}
+
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 }
 
@@ -936,16 +948,19 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
 	struct spi_device *spi = msg->spi;
 	int ret;
 	bool skip = false;
+	int single_xfer;
 
 	msg->status = 0;
 	msg->actual_length = 0;
 
+	single_xfer = list_is_singular(&msg->transfers);
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 		u32 cmd1;
 
 		reinit_completion(&tspi->xfer_completion);
 
-		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
+		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
+						    single_xfer);
 
 		if (!xfer->len) {
 			ret = 0;
-- 
2.7.4


  parent reply	other threads:[~2019-05-14  5:04 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-14  5:03 [PATCH V5 0/4] additional features to Tegra SPI Sowjanya Komatineni
2019-05-14  5:03 ` [PATCH V5 1/4] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
2019-05-14  9:33   ` Jon Hunter
2019-05-14 17:18     ` Sowjanya Komatineni
2019-05-14 17:31       ` Jon Hunter
2019-05-15  9:35       ` Mark Brown
2019-05-15 11:24         ` Sowjanya Komatineni
2019-05-15 11:29           ` Mark Brown
     [not found]             ` <BYAPR12MB3398528B86D3DE9CC3AA6D85C2090@BYAPR12MB3398.namprd12.prod.outlook.com>
2019-05-15 11:42               ` Mark Brown
2019-05-15 11:18   ` Applied "spi: tegra114: add support for gpio based CS" to the spi tree Mark Brown
2019-05-14  5:03 ` Sowjanya Komatineni [this message]
2019-05-15 11:18   ` Applied "spi: tegra114: add support for hw based cs" " Mark Brown
2019-05-14  5:03 ` [PATCH V5 3/4] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for HW CS timing" to the spi tree Mark Brown
2019-05-14  5:03 ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni
2019-05-15 11:18   ` Applied "spi: tegra114: add support for TX and RX trimmers" to the spi tree Mark Brown
2019-05-23  1:02   ` [PATCH V5 4/4] spi: tegra114: add support for TX and RX trimmers Nathan Chancellor
2019-05-23  1:10     ` Sowjanya Komatineni

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