From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A11DC04AB6 for ; Mon, 3 Jun 2019 03:51:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EBC7627B2A for ; Mon, 3 Jun 2019 03:51:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726820AbfFCDv3 (ORCPT ); Sun, 2 Jun 2019 23:51:29 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:59978 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725872AbfFCDv0 (ORCPT ); Sun, 2 Jun 2019 23:51:26 -0400 X-UUID: 272faaeb3fc94f5f9dc3c300a4f79ecc-20190603 X-UUID: 272faaeb3fc94f5f9dc3c300a4f79ecc-20190603 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 424188288; Mon, 03 Jun 2019 11:51:19 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 3 Jun 2019 11:51:18 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 3 Jun 2019 11:51:17 +0800 From: Qii Wang To: CC: , , , , , , , , , , , Subject: [PATCH 1/2] dt-bindings: i3c: Document MediaTek I3C master bindings Date: Mon, 3 Jun 2019 11:51:02 +0800 Message-ID: <1559533863-10292-2-git-send-email-qii.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1559533863-10292-1-git-send-email-qii.wang@mediatek.com> References: <1559533863-10292-1-git-send-email-qii.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document MediaTek I3C master DT bindings. Signed-off-by: Qii Wang --- .../devicetree/bindings/i3c/mtk,i3c-master.txt | 50 ++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt diff --git a/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt new file mode 100644 index 0000000..89ec380 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt @@ -0,0 +1,50 @@ +Bindings for MediaTek I3C master block +===================================== + +Required properties: +-------------------- +- compatible: shall be "mediatek,i3c-master" +- reg: physical base address of the controller and apdma base, length of + memory mapped region. +- reg-names: should be "main" for controller and "dma" for apdma. +- interrupts: interrupt number to the cpu. +- clock-div: the fixed value for frequency divider of clock source in i3c + module. Each IC may be different. +- clocks: clock name from clock manager. +- clock-names: must include "main" and "dma". + +Mandatory properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- #address-cells: shall be set to 3 +- #size-cells: shall be set to 0 + +Optional properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- i2c-scl-hz +- i3c-scl-hz + +I3C device connected on the bus follow the generic description (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details). + +Example: + + i3c0: i3c@1100d000 { + compatible = "mediatek,i3c-master"; + reg = <0x1100d000 0x100>, + <0x11000300 0x80>; + reg-names = "main", "dma"; + interrupts = ; + clock-div = <16>; + clocks = <&i3c0_ck>, <&ap_dma_ck>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-hz = <100000>; + + nunchuk: nunchuk@52 { + compatible = "nintendo,nunchuk"; + reg = <0x52 0x80000010 0>; + }; + }; -- 1.7.9.5