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From: Yuti Amonkar <yamonkar@cadence.com>
To: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<kishon@ti.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<maxime@cerno.tech>
Cc: <jsarha@ti.com>, <tomi.valkeinen@ti.com>, <praneeth@ti.com>,
	<mparab@cadence.com>, <sjakhade@cadence.com>,
	<yamonkar@cadence.com>
Subject: [PATCH v4 02/13] dt-bindings: phy: Add Cadence MHDP PHY bindings in YAML format.
Date: Thu, 6 Feb 2020 07:10:50 +0100	[thread overview]
Message-ID: <1580969461-16981-3-git-send-email-yamonkar@cadence.com> (raw)
In-Reply-To: <1580969461-16981-1-git-send-email-yamonkar@cadence.com>

- Add Cadence MHDP PHY bindings in YAML format.
- Add Torrent PHY reference clock bindings.
- Add sub-node bindings for each group of PHY lanes based on PHY type.
  Each sub-node includes properties such as master lane number, link reset,
  phy type, number of lanes etc.
- Add reset support including PHY reset and individual lane reset.
- Add a new compatible string used for TI SoCs using Torrent PHY.
This will not affect ABI as the driver has never been functional,
and therefore do not exist in any active use case.

Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
---
 .../bindings/phy/phy-cadence-torrent.yaml     | 143 ++++++++++++++++++
 1 file changed, 143 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
new file mode 100644
index 000000000000..9f94be1dce6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence Torrent SD0801 PHY binding for DisplayPort
+
+description:
+  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
+  hardware included with the Cadence MHDP DisplayPort controller.
+
+maintainers:
+  - Swapnil Jakhade <sjakhade@cadence.com>
+  - Yuti Amonkar <yamonkar@cadence.com>
+
+properties:
+  compatible:
+    enum:
+      - cdns,torrent-phy
+      - ti,j721e-serdes-10g
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+  clocks:
+    maxItems: 1
+    description:
+      PHY reference clock. Must contain an entry in clock-names.
+
+  clock-names:
+    const: refclk
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: Offset of the Torrent PHY configuration registers.
+      - description: Offset of the DPTX PHY configuration registers.
+
+  reg-names:
+    minItems: 1
+    maxItems: 2
+    items:
+      - const: torrent_phy
+      - const: dptx_phy
+
+  resets:
+    maxItems: 1
+    description:
+      Torrent PHY reset.
+      See Documentation/devicetree/bindings/reset/reset.txt
+
+patternProperties:
+  '^phy@[0-7]+$':
+    type: object
+    description:
+      Each group of PHY lanes with a single master lane should be represented as a sub-node.
+    properties:
+      reg:
+        description:
+          The master lane number. This is the lowest numbered lane in the lane group.
+
+      resets:
+        minItems: 1
+        maxItems: 4
+        description:
+          Contains list of resets, one per lane, to get all the link lanes out of reset.
+
+      "#phy-cells":
+        const: 0
+
+      cdns,phy-type:
+        description:
+          Specifies the type of PHY for which the group of PHY lanes is used.
+          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+          - enum: [1, 2, 3, 4, 5, 6]
+
+      cdns,num-lanes:
+        description:
+          Number of DisplayPort lanes.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+          - enum: [1, 2, 4]
+        default: 4
+
+      cdns,max-bit-rate:
+        description:
+          Maximum DisplayPort link bit rate to use, in Mbps
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+          - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
+        default: 8100
+
+    required:
+      - reg
+      - resets
+      - "#phy-cells"
+      - cdns,phy-type
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/phy/phy.h>
+    torrent_phy: phy@f0fb500000 {
+          compatible = "cdns,torrent-phy";
+          reg = <0xf0 0xfb500000 0x0 0x00100000>,
+                <0xf0 0xfb030a00 0x0 0x00000040>;
+          reg-names = "torrent_phy", "dptx_phy";
+          resets = <&phyrst 0>;
+          clocks = <&ref_clk>;
+          clock-names = "refclk";
+          #address-cells = <1>;
+          #size-cells = <0>;
+          torrent_phy_dp: phy@0 {
+                    reg = <0>;
+                    resets = <&phyrst 1>, <&phyrst 2>,
+                             <&phyrst 3>, <&phyrst 4>;
+                    #phy-cells = <0>;
+                    cdns,phy-type = <PHY_TYPE_DP>;
+                    cdns,num-lanes = <4>;
+                    cdns,max-bit-rate = <8100>;
+          };
+    };
+...
-- 
2.20.1


  parent reply	other threads:[~2020-02-06  6:12 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-06  6:10 [PATCH v4 00/13] PHY: Update Cadence Torrent PHY driver with reconfiguration Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 01/13] dt-bindings: phy: Remove Cadence MHDP PHY dt binding Yuti Amonkar
2020-02-06 21:51   ` Rob Herring
2020-02-06  6:10 ` Yuti Amonkar [this message]
2020-02-06 20:55   ` [PATCH v4 02/13] dt-bindings: phy: Add Cadence MHDP PHY bindings in YAML format Rob Herring
2020-02-07 12:05     ` Yuti Suresh Amonkar
2020-02-10 12:10     ` Jyri Sarha
2020-03-11 19:53   ` Rob Herring
2020-02-06  6:10 ` [PATCH v4 03/13] phy: cadence-dp: Rename to phy-cadence-torrent Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 04/13] phy: cadence-torrent: Adopt Torrent nomenclature Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 05/13] phy: cadence-torrent: Add wrapper for PHY register access Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 06/13] phy: cadence-torrent: Add wrapper for DPTX " Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 07/13] phy: cadence-torrent: Refactor code for reusability Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 08/13] phy: cadence-torrent: Add 19.2 MHz reference clock support Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 09/13] phy: cadence-torrent: Implement PHY configure APIs Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 10/13] phy: cadence-torrent: Use regmap to read and write Torrent PHY registers Yuti Amonkar
2020-02-06  6:10 ` [PATCH v4 11/13] phy: cadence-torrent: Use regmap to read and write DPTX " Yuti Amonkar
2020-02-06  6:11 ` [PATCH v4 12/13] phy: cadence-torrent: Add platform dependent initialization structure Yuti Amonkar
2020-02-06  6:11 ` [PATCH v4 13/13] phy: cadence-torrent: Add support for subnode bindings Yuti Amonkar
2020-03-04 12:05 ` [PATCH v4 00/13] PHY: Update Cadence Torrent PHY driver with reconfiguration Kishon Vijay Abraham I

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