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From: Sayali Lokhande <sayalil@codeaurora.org>
To: bjorn.andersson@linaro.org, adrian.hunter@intel.com,
	robh+dt@kernel.org, ulf.hansson@linaro.org,
	asutoshd@codeaurora.org, stummala@codeaurora.org,
	ppvk@codeaurora.org, rampraka@codeaurora.org,
	vbadigan@codeaurora.org, sboyd@kernel.org,
	georgi.djakov@linaro.org, mka@chromium.org
Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	agross@kernel.org, linux-mmc-owner@vger.kernel.org,
	Sayali Lokhande <sayalil@codeaurora.org>
Subject: [PATCH RFC] Toggle fifo write clk after ungating sdcc clk
Date: Thu, 20 Feb 2020 14:50:45 +0530	[thread overview]
Message-ID: <1582190446-4778-1-git-send-email-sayalil@codeaurora.org> (raw)

During GCC level clock gating of MCLK, the async FIFO
gets into some hang condition, such that for the next
transfer after MCLK ungating, first bit of CMD response
doesn't get written in to the FIFO. This cause the CPSM
to hang eventually leading to SW timeout.

To fix the issue, toggle the FIFO write clock after
MCLK ungated to get the FIFO pointers and flags to
valid states.

Ram Prakash Gupta (1):
  mmc: sdhci-msm: Toggle fifo write clk after ungating sdcc clk

 drivers/mmc/host/sdhci-msm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

             reply	other threads:[~2020-02-20  9:21 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-20  9:20 Sayali Lokhande [this message]
2020-02-20  9:20 ` [PATCH RFC] mmc: sdhci-msm: " Sayali Lokhande
2020-02-20 15:44   ` Bjorn Andersson
2020-02-20 18:02   ` Stephen Boyd
2020-02-24 13:49   ` Veerabhadrarao Badiganti
2020-02-28  6:54     ` Sayali Lokhande
2020-02-20 15:51 ` [PATCH RFC] " Bjorn Andersson

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