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From: Stephen Boyd <sboyd@kernel.org>
To: Sayali Lokhande <sayalil@codeaurora.org>,
	adrian.hunter@intel.com, asutoshd@codeaurora.org,
	bjorn.andersson@linaro.org, georgi.djakov@linaro.org,
	mka@chromium.org, ppvk@codeaurora.org, rampraka@codeaurora.org,
	robh+dt@kernel.org, stummala@codeaurora.org,
	ulf.hansson@linaro.org, vbadigan@codeaurora.org
Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	agross@kernel.org, linux-mmc-owner@vger.kernel.org,
	Sayali Lokhande <sayalil@codeaurora.org>
Subject: Re: [PATCH RFC] mmc: sdhci-msm: Toggle fifo write clk after ungating sdcc clk
Date: Thu, 20 Feb 2020 10:02:50 -0800	[thread overview]
Message-ID: <158222177078.184098.4974715009961694108@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1582190446-4778-2-git-send-email-sayalil@codeaurora.org>

Quoting Sayali Lokhande (2020-02-20 01:20:46)
> From: Ram Prakash Gupta <rampraka@codeaurora.org>
> 
> During GCC level clock gating of MCLK, the async FIFO

Is this automatic hardware clock gating?

> gets into some hang condition, such that for the next
> transfer after MCLK ungating, first bit of CMD response
> doesn't get written in to the FIFO. This cause the CPSM
> to hang eventually leading to SW timeout.
> 
> To fix the issue, toggle the FIFO write clock after
> MCLK ungated to get the FIFO pointers and flags to
> valid states.
> 
> Change-Id: Ibef2d1d283ac0b6983c609a4abc98bc574d31fa6
> Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
> Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
> ---
>  drivers/mmc/host/sdhci-msm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index c3a160c..eaa3e95 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -1554,6 +1556,43 @@ static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>         sdhci_enable_clk(host, clk);
>  }
>  
> +/*
> + * After MCLK ugating, toggle the FIFO write clock to get

What is ugating?

> + * the FIFO pointers and flags to valid state.
> + */
> +static void sdhci_msm_toggle_fifo_write_clk(struct sdhci_host *host)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> +       const struct sdhci_msm_offset *msm_offset =
> +                                       msm_host->offset;
> +       struct mmc_card *card = host->mmc->card;
> +
> +       if (msm_host->tuning_done ||
> +                       (card && card->ext_csd.strobe_support &&
> +                       card->host->ios.enhanced_strobe)) {
> +               /*
> +                * set HC_REG_DLL_CONFIG_3[1] to select MCLK as
> +                * DLL input clock
> +                */

  parent reply	other threads:[~2020-02-20 18:02 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-20  9:20 [PATCH RFC] " Sayali Lokhande
2020-02-20  9:20 ` [PATCH RFC] mmc: sdhci-msm: " Sayali Lokhande
2020-02-20 15:44   ` Bjorn Andersson
2020-02-20 18:02   ` Stephen Boyd [this message]
2020-02-24 13:49   ` Veerabhadrarao Badiganti
2020-02-28  6:54     ` Sayali Lokhande
2020-02-20 15:51 ` [PATCH RFC] " Bjorn Andersson

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