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[60.241.117.97]) by smtp.gmail.com with ESMTPSA id o15sm11699220pgj.60.2020.04.06.17.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 17:51:44 -0700 (PDT) Date: Tue, 07 Apr 2020 10:50:20 +1000 From: Nicholas Piggin Subject: Re: [RFC PATCH v3 05/15] powerpc/irq: Add helpers to get and set regs->softe To: Benjamin Herrenschmidt , Christophe Leroy , Michael Ellerman , msuchanek@suse.de, Paul Mackerras Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org References: <5aeaa33383e833f6eca30893fbd188b88e019eaa.1586196948.git.christophe.leroy@c-s.fr> In-Reply-To: MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Message-Id: <1586219567.cl8bye6kgu.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Christophe Leroy's on April 7, 2020 4:16 am: > regs->softe doesn't exist on PPC32. >=20 > Add helpers to get and set regs->softe. > Those helpers will void on PPC32. >=20 > Signed-off-by: Christophe Leroy > --- > arch/powerpc/include/asm/hw_irq.h | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm= /hw_irq.h > index e0e71777961f..e69466867d5f 100644 > --- a/arch/powerpc/include/asm/hw_irq.h > +++ b/arch/powerpc/include/asm/hw_irq.h > @@ -39,6 +39,8 @@ > #define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE) > #endif > =20 > +#endif /* CONFIG_PPC64 */ > + > /* > * flags for paca->irq_soft_mask > */ > @@ -47,8 +49,6 @@ > #define IRQS_PMI_DISABLED 2 > #define IRQS_ALL_DISABLED (IRQS_DISABLED | IRQS_PMI_DISABLED) > =20 > -#endif /* CONFIG_PPC64 */ > - > #ifndef __ASSEMBLY__ > =20 > extern void replay_system_reset(void); > @@ -282,6 +282,15 @@ extern void irq_set_pending_from_srr1(unsigned long = srr1); > =20 > extern void force_external_irq_replay(void); > =20 > +static inline unsigned long get_softe(struct pt_regs *regs) > +{ > + return regs->softe; > +} > + > +static inline void set_softe(struct pt_regs *regs, unsigned long val) > +{ > + regs->softe =3D val; > +} > #else /* CONFIG_PPC64 */ > =20 > static inline unsigned long arch_local_save_flags(void) > @@ -350,6 +359,14 @@ static inline bool arch_irq_disabled_regs(struct pt_= regs *regs) > =20 > static inline void may_hard_irq_enable(void) { } > =20 > +static inline unsigned long get_softe(struct pt_regs *regs) > +{ > + return 0; > +} > + > +static inline void set_softe(struct pt_regs *regs, unsigned long val) > +{ > +} If this goes into a general shared header, I would prefer if we could do something a bit more general (at least with the name). I think get_softe() could just be replaced with arch_irq_disabled_regs(). For set, could we call it irq_soft_mask_regs_set_state()? 32 has no soft mask state in regs, so it's more obvious that it's a no-op. Or you could make 32-bit version a BUG(), and then always guard it with IS_ENABLED(). Thanks, Nick =