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From: CK Hu <ck.hu@mediatek.com>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: Frank Wunderlich <linux@fw-web.de>,
	"moderated list:ARM/Mediatek SoC support" 
	<linux-mediatek@lists.infradead.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Enric Balletbo i Serra <enric.balletbo@collabora.com>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	lkml <linux-kernel@vger.kernel.org>, <stable@vger.kernel.org>,
	Frank Wunderlich <frank-w@public-files.de>
Subject: Re: [PATCH] soc: mmsys: mediatek: add mask to mmsys routes
Date: Thu, 29 Jul 2021 11:42:31 +0800	[thread overview]
Message-ID: <1627530151.32756.9.camel@mtksdaap41> (raw)
In-Reply-To: <CAJMQK-g8g5QJbBkU-A6th1VSWafxVv2fGtym+enQa_hDVaVoBw@mail.gmail.com>

Hi, Hsin-yi:

On Thu, 2021-07-29 at 11:15 +0800, Hsin-Yi Wang wrote:
> On Wed, Jul 28, 2021 at 1:41 AM Frank Wunderlich <linux@fw-web.de> wrote:
> >
> > From: CK Hu <ck.hu@mediatek.com>
> >
> > SOUT has many bits and need to be cleared before set new value.
> > Write only could do the clear, but for MOUT, it clears bits that
> > should not be cleared. So use a mask to reset only the needed bits.
> >
> > this fixes HDMI issues on MT7623/BPI-R2 since 5.13
> >
> > Cc: stable@vger.kernel.org
> > Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers")
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > Signed-off-by: CK Hu <ck.hu@mediatek.com>
> > ---
> > code is taken from here (upstreamed without mask part)
> > https://urldefense.com/v3/__https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/*/2345186/5__;Kw!!CTRNKA9wMg0ARbw!1ebx2FjrHnqvOqw3HdVyMMYcEUivNbxRIOi1_DXMWwfxJHx45NyKI-Dt4Mvo1g$ 
> > basicly CK Hu's code so i set him as author
> > ---
> >  drivers/soc/mediatek/mtk-mmsys.c |   7 +-
> >  drivers/soc/mediatek/mtk-mmsys.h | 133 +++++++++++++++++++++----------
> >  2 files changed, 98 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> > index 080660ef11bf..0f949896fd06 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -68,7 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> >
> >         for (i = 0; i < mmsys->data->num_routes; i++)
> >                 if (cur == routes[i].from_comp && next == routes[i].to_comp) {
> > -                       reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val;
> > +                       reg = readl_relaxed(mmsys->regs + routes[i].addr);
> > +                       reg &= ~routes[i].mask;
> > +                       reg |= routes[i].val;
> >                         writel_relaxed(reg, mmsys->regs + routes[i].addr);
> >                 }
> >  }
> > @@ -85,7 +87,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> >
> >         for (i = 0; i < mmsys->data->num_routes; i++)
> >                 if (cur == routes[i].from_comp && next == routes[i].to_comp) {
> > -                       reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val;
> > +                       reg = readl_relaxed(mmsys->regs + routes[i].addr);
> > +                       reg &= ~routes[i].mask;
> 
> This patch is breaking the mt8183 internal display. I think it's
> because  ~routes[i].val; is removed?
> Also what should the routes[i].mask be if it's not set in
> mmsys_mt8183_routing_table?

I'm not sure this problem is about MOUT or SOUT. But for MOUT, it's not
necessary to set mask because the value is equal to mask. To make thins
simple, the code could be

/* For MOUT,  value is equal to mask, so mask is 0 and clear the value
*/
reg &= ~routes[i].mask & ~routes[i].val;

Regards,
CK
> 
> >                         writel_relaxed(reg, mmsys->regs + routes[i].addr);
> >                 }
> >  }
> <snip>


  reply	other threads:[~2021-07-29  3:42 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-27 17:40 Frank Wunderlich
2021-07-28 23:37 ` Chun-Kuang Hu
2021-07-29  3:15 ` Hsin-Yi Wang
2021-07-29  3:42   ` CK Hu [this message]
2021-07-29  5:40   ` Frank Wunderlich
2021-07-29  5:47     ` Hsin-Yi Wang
2021-07-29  5:53       ` Frank Wunderlich
2021-07-29  5:58         ` Hsin-Yi Wang
2021-07-29  6:45           ` Frank Wunderlich
2021-07-29  6:47             ` Hsin-Yi Wang

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