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From: Rajesh Patil <rajpat@codeaurora.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: swboyd@chromium.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com, skakit@codeaurora.org, Roja Rani Yarubandi <rojay@codeaurora.org>, Rajesh Patil <rajpat@codeaurora.org> Subject: [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node Date: Thu, 12 Aug 2021 13:11:15 +0530 [thread overview] Message-ID: <1628754078-29779-5-git-send-email-rajpat@codeaurora.org> (raw) In-Reply-To: <1628754078-29779-1-git-send-email-rajpat@codeaurora.org> From: Roja Rani Yarubandi <rojay@codeaurora.org> Update the compatible string as "qcom,geni-uart". Add interconnects and power-domains. Split the pinctrl functions and correct the gpio pins. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e461395..2dc7e8c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -861,13 +861,18 @@ }; uart5: serial@994000 { - compatible = "qcom,geni-debug-uart"; + compatible = "qcom,geni-uart"; reg = <0 0x00994000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_default>; + pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -2255,9 +2260,24 @@ function = "qup04"; }; - qup_uart5_default: qup-uart5-default { - pins = "gpio46", "gpio47"; - function = "qup13"; + qup_uart5_cts: qup-uart5-cts { + pins = "gpio20"; + function = "qup05"; + }; + + qup_uart5_rts: qup-uart5-rts { + pins = "gpio21"; + function = "qup05"; + }; + + qup_uart5_tx: qup-uart5-tx { + pins = "gpio22"; + function = "qup05"; + }; + + qup_uart5_rx: qup-uart5-rx { + pins = "gpio23"; + function = "qup05"; }; qup_uart6_cts: qup-uart6-cts { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2021-08-12 7:42 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil 2021-08-12 7:41 ` [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node Rajesh Patil 2021-08-12 13:09 ` Matthias Kaehlcke 2021-08-26 12:59 ` rajpat 2021-09-03 15:46 ` Matthias Kaehlcke 2021-08-12 7:41 ` [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil 2021-08-12 13:15 ` Matthias Kaehlcke 2021-08-23 11:44 ` rajpat 2021-08-12 7:41 ` [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil 2021-08-12 14:14 ` Matthias Kaehlcke 2021-08-12 16:22 ` Matthias Kaehlcke 2021-08-26 13:07 ` rajpat 2021-08-26 19:51 ` Matthias Kaehlcke 2021-09-01 7:06 ` rajpat 2021-08-19 0:04 ` Doug Anderson 2021-08-26 12:53 ` rajpat 2021-08-12 7:41 ` Rajesh Patil [this message] 2021-08-12 15:46 ` [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node Matthias Kaehlcke 2021-08-12 7:41 ` [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp Rajesh Patil 2021-08-12 16:05 ` Matthias Kaehlcke 2021-08-26 13:07 ` rajpat 2021-08-12 7:41 ` [PATCH V5 6/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil 2021-08-12 19:22 ` Matthias Kaehlcke 2021-08-12 7:41 ` [PATCH V5 7/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
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