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From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
	like.xu.linux@gmail.com, vkuznets@redhat.com,
	wei.w.wang@intel.com, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v8 15/15] KVM: x86/cpuid: Advise Arch LBR feature in CPUID
Date: Tue, 24 Aug 2021 15:56:17 +0800	[thread overview]
Message-ID: <1629791777-16430-16-git-send-email-weijiang.yang@intel.com> (raw)
In-Reply-To: <1629791777-16430-1-git-send-email-weijiang.yang@intel.com>

Add Arch LBR feature bit in CPU cap-mask to expose the feature.
Only max LBR depth is supported for guest, and it's consistent
with host Arch LBR settings.

Co-developed-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
 arch/x86/kvm/cpuid.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 03025eea1524..d98ebefd5d72 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -88,6 +88,16 @@ static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent)
 		if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
 			return -EINVAL;
 	}
+	best = cpuid_entry2_find(entries, nent, 0x1c, 0);
+	if (best) {
+		unsigned int eax, ebx, ecx, edx;
+
+		/* Reject user-space CPUID if depth is different from host's.*/
+		cpuid_count(0x1c, 0, &eax, &ebx, &ecx, &edx);
+
+		if ((best->eax & 0xff) != BIT(fls(eax & 0xff) - 1))
+			return -EINVAL;
+	}
 
 	return 0;
 }
@@ -490,7 +500,7 @@ void kvm_set_cpu_caps(void)
 		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
 		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
 		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
-		F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16)
+		F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | F(ARCH_LBR)
 	);
 
 	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
@@ -903,6 +913,27 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 				goto out;
 		}
 		break;
+	/* Architectural LBR */
+	case 0x1c: {
+		u32 lbr_depth_mask = entry->eax & 0xff;
+
+		if (!lbr_depth_mask ||
+		    !kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) {
+			entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
+			break;
+		}
+		/*
+		 * KVM only exposes the maximum supported depth, which is the
+		 * fixed value used on the host side.
+		 * KVM doesn't allow VMM userspace to adjust LBR depth because
+		 * guest LBR emulation depends on the configuration of host LBR
+		 * driver.
+		 */
+		lbr_depth_mask = BIT((fls(lbr_depth_mask) - 1));
+		entry->eax &= ~0xff;
+		entry->eax |= lbr_depth_mask;
+		break;
+	}
 	case KVM_CPUID_SIGNATURE: {
 		static const char signature[12] = "KVMKVMKVM\0\0";
 		const u32 *sigptr = (const u32 *)signature;
-- 
2.25.1


  parent reply	other threads:[~2021-08-24  7:43 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-24  7:56 [PATCH v8 00/15] Introduce Architectural LBR for vPMU Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 01/15] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 02/15] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 03/15] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 04/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 05/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2021-08-25  7:59   ` kernel test robot
2021-08-27  1:06   ` kernel test robot
2021-08-24  7:56 ` [PATCH v8 06/15] KVM: x86/pmu: Refactor code to support " Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 07/15] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 08/15] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 09/15] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 10/15] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 11/15] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 12/15] KVM: nVMX: Add necessary Arch LBR settings for nested VM Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 13/15] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest Yang Weijiang
2021-08-24  7:56 ` [PATCH v8 14/15] KVM: x86/vmx: Flip Arch LBREn bit on guest state change Yang Weijiang
2021-08-24  7:56 ` Yang Weijiang [this message]
2021-10-15  0:01   ` [PATCH v8 15/15] KVM: x86/cpuid: Advise Arch LBR feature in CPUID Sean Christopherson
2021-10-15  1:28     ` Yang Weijiang
2021-10-15  2:05       ` Like Xu
2021-10-15 14:49         ` Sean Christopherson
2021-09-07  3:26 ` [PATCH v8 00/15] Introduce Architectural LBR for vPMU Yang Weijiang

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