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From: "tip-bot2 for 周琰杰" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: zhouyanjie@wanyeetech.com, Paul Cercueil <paul@crapouillou.net>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: timers/core] clocksource/drivers/ingenic: Use bitfield macro helpers
Date: Thu, 26 Aug 2021 16:25:16 -0000	[thread overview]
Message-ID: <162999511697.25758.16027378854390463391.tip-bot2@tip-bot2> (raw)
In-Reply-To: <1627638188-116163-1-git-send-email-zhouyanjie@wanyeetech.com>

The following commit has been merged into the timers/core branch of tip:

Commit-ID:     3b87265d825a2d29eb6b67511f0e7ed62225cd97
Gitweb:        https://git.kernel.org/tip/3b87265d825a2d29eb6b67511f0e7ed62225cd97
Author:        周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
AuthorDate:    Fri, 30 Jul 2021 17:43:08 +08:00
Committer:     Daniel Lezcano <daniel.lezcano@linaro.org>
CommitterDate: Sat, 14 Aug 2021 02:44:35 +02:00

clocksource/drivers/ingenic: Use bitfield macro helpers

Use "FIELD_GET()" and "FIELD_PREP()" to simplify the code.

[dlezcano] : Changed title

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/1627638188-116163-1-git-send-email-zhouyanjie@wanyeetech.com
---
 drivers/clocksource/ingenic-sysost.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/clocksource/ingenic-sysost.c b/drivers/clocksource/ingenic-sysost.c
index a129840..cb6fc2f 100644
--- a/drivers/clocksource/ingenic-sysost.c
+++ b/drivers/clocksource/ingenic-sysost.c
@@ -4,6 +4,7 @@
  * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
@@ -34,8 +35,6 @@
 /* bits within the OSTCCR register */
 #define OSTCCR_PRESCALE1_MASK	0x3
 #define OSTCCR_PRESCALE2_MASK	0xc
-#define OSTCCR_PRESCALE1_LSB	0
-#define OSTCCR_PRESCALE2_LSB	2
 
 /* bits within the OSTCR register */
 #define OSTCR_OST1CLR			BIT(0)
@@ -98,7 +97,7 @@ static unsigned long ingenic_ost_percpu_timer_recalc_rate(struct clk_hw *hw,
 
 	prescale = readl(ost_clk->ost->base + info->ostccr_reg);
 
-	prescale = (prescale & OSTCCR_PRESCALE1_MASK) >> OSTCCR_PRESCALE1_LSB;
+	prescale = FIELD_GET(OSTCCR_PRESCALE1_MASK, prescale);
 
 	return parent_rate >> (prescale * 2);
 }
@@ -112,7 +111,7 @@ static unsigned long ingenic_ost_global_timer_recalc_rate(struct clk_hw *hw,
 
 	prescale = readl(ost_clk->ost->base + info->ostccr_reg);
 
-	prescale = (prescale & OSTCCR_PRESCALE2_MASK) >> OSTCCR_PRESCALE2_LSB;
+	prescale = FIELD_GET(OSTCCR_PRESCALE2_MASK, prescale);
 
 	return parent_rate >> (prescale * 2);
 }
@@ -151,7 +150,8 @@ static int ingenic_ost_percpu_timer_set_rate(struct clk_hw *hw, unsigned long re
 	int val;
 
 	val = readl(ost_clk->ost->base + info->ostccr_reg);
-	val = (val & ~OSTCCR_PRESCALE1_MASK) | (prescale << OSTCCR_PRESCALE1_LSB);
+	val &= ~OSTCCR_PRESCALE1_MASK;
+	val |= FIELD_PREP(OSTCCR_PRESCALE1_MASK, prescale);
 	writel(val, ost_clk->ost->base + info->ostccr_reg);
 
 	return 0;
@@ -166,7 +166,8 @@ static int ingenic_ost_global_timer_set_rate(struct clk_hw *hw, unsigned long re
 	int val;
 
 	val = readl(ost_clk->ost->base + info->ostccr_reg);
-	val = (val & ~OSTCCR_PRESCALE2_MASK) | (prescale << OSTCCR_PRESCALE2_LSB);
+	val &= ~OSTCCR_PRESCALE2_MASK;
+	val |= FIELD_PREP(OSTCCR_PRESCALE2_MASK, prescale);
 	writel(val, ost_clk->ost->base + info->ostccr_reg);
 
 	return 0;

      parent reply	other threads:[~2021-08-26 16:26 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-30  9:43 [PATCH v2] clocksource: Ingenic: Improve the code 周琰杰 (Zhou Yanjie)
2021-07-30 19:00 ` Paul Cercueil
2021-08-26 16:25 ` tip-bot2 for 周琰杰 [this message]

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