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From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Pali Rohár" <pali@kernel.org>, "Marc Zyngier" <maz@kernel.org>
Cc: Masami Hiramatsu <mhiramat@kernel.org>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH v2 2/2] PCI: uniphier: Serialize INTx masking/unmasking
Date: Mon, 30 Aug 2021 11:22:38 +0900 [thread overview]
Message-ID: <1630290158-31264-3-git-send-email-hayashi.kunihiko@socionext.com> (raw)
In-Reply-To: <1630290158-31264-1-git-send-email-hayashi.kunihiko@socionext.com>
The condition register PCI_RCV_INTX is used in irq_mask() and irq_unmask()
callbacks. Accesses to register can occur at the same time without a lock.
Add a lock into each callback to prevent the issue.
Fixes: 7e6d5cd88a6f ("PCI: uniphier: Add UniPhier PCIe host controller support")
Suggested-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/controller/dwc/pcie-uniphier.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
index 26f630c..0ddeec0 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -186,11 +186,16 @@ static void uniphier_pcie_irq_mask(struct irq_data *d)
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ unsigned long flags;
u32 val;
+ raw_spin_lock_irqsave(&pp->lock, flags);
+
val = readl(priv->base + PCL_RCV_INTX);
val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
writel(val, priv->base + PCL_RCV_INTX);
+
+ raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static void uniphier_pcie_irq_unmask(struct irq_data *d)
@@ -198,11 +203,16 @@ static void uniphier_pcie_irq_unmask(struct irq_data *d)
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ unsigned long flags;
u32 val;
+ raw_spin_lock_irqsave(&pp->lock, flags);
+
val = readl(priv->base + PCL_RCV_INTX);
val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
writel(val, priv->base + PCL_RCV_INTX);
+
+ raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static struct irq_chip uniphier_pcie_irq_chip = {
--
2.7.4
next prev parent reply other threads:[~2021-08-30 2:23 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-30 2:22 [PATCH v2 0/2] PCI: uniphier: Fix " Kunihiko Hayashi
2021-08-30 2:22 ` [PATCH v2 1/2] PCI: uniphier: Fix INTx mask/unmask bit operation and remove ack function Kunihiko Hayashi
2021-08-30 15:59 ` Pali Rohár
2021-08-30 2:22 ` Kunihiko Hayashi [this message]
2021-09-16 11:30 ` [PATCH v2 0/2] PCI: uniphier: Fix INTx masking/unmasking Kunihiko Hayashi
2021-09-17 13:54 ` Marc Zyngier
2021-09-17 23:48 ` Kunihiko Hayashi
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