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From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, marcel.ziswiler@toradex.com,
	tharvey@gateworks.com, kishon@ti.com, vkoul@kernel.org,
	robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v4 2/8] dt-bindings: phy: Add imx8 pcie phy driver support
Date: Thu, 28 Oct 2021 15:27:11 +0800	[thread overview]
Message-ID: <1635406037-20900-3-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1635406037-20900-1-git-send-email-hongxing.zhu@nxp.com>

Add dt-binding for the standalone i.MX8 PCIe PHY driver.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
 .../bindings/phy/fsl,imx8-pcie-phy.yaml       | 95 +++++++++++++++++++
 1 file changed, 95 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
new file mode 100644
index 000000000000..b9f89e343b0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings
+
+maintainers:
+  - Richard Zhu <hongxing.zhu@nxp.com>
+
+properties:
+  "#phy-cells":
+    const: 0
+
+  compatible:
+    enum:
+      - fsl,imx8mm-pcie-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: PHY module clock
+
+  clock-names:
+    items:
+      - const: ref
+
+  resets:
+    items:
+      - description: Phandles to PCIe-related reset lines exposed by SRC
+          IP block.
+
+  reset-names:
+    items:
+      - const: pciephy
+
+  fsl,refclk-pad-mode:
+    description: |
+      Specifies the mode of the refclk pad used. It can be UNUSED(PHY
+      refclock is derived from SoC internal source), INPUT(PHY refclock
+      is provided externally via the refclk pad) or OUTPUT(PHY refclock
+      is derived from SoC internal source and provided on the refclk pad).
+      Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
+      to be used.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 0, 1, 2 ]
+
+  fsl,tx-deemph-gen1:
+    description: Gen1 De-emphasis value (optional required).
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  fsl,tx-deemph-gen2:
+    description: Gen2 De-emphasis value (optional required).
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  fsl,clkreq-unsupported:
+    type: boolean
+    description: A boolean property indicating the CLKREQ# signal is
+      not supported in the board design (optional)
+
+required:
+  - "#phy-cells"
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - fsl,refclk-pad-mode
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/phy/phy-imx8-pcie.h>
+    #include <dt-bindings/reset/imx8mq-reset.h>
+
+    pcie_phy: pcie-phy@32f00000 {
+            compatible = "fsl,imx8mm-pcie-phy";
+            reg = <0x32f00000 0x10000>;
+            clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+            clock-names = "ref";
+            assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+            assigned-clock-rates = <100000000>;
+            assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
+            resets = <&src IMX8MQ_RESET_PCIEPHY>;
+            reset-names = "pciephy";
+            fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+            #phy-cells = <0>;
+    };
+...
-- 
2.25.1


  parent reply	other threads:[~2021-10-28  7:53 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-28  7:27 [PATCH v4 0/8] add the imx8m pcie phy driver and imx8mm pcie support Richard Zhu
2021-10-28  7:27 ` [PATCH v4 1/8] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy Richard Zhu
2021-10-28  7:27 ` Richard Zhu [this message]
2021-10-28  7:27 ` [PATCH v4 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties Richard Zhu
2021-10-28  7:27 ` [PATCH v4 4/8] arm64: dts: imx8mm: Add the pcie phy support Richard Zhu
2021-10-28  7:27 ` [PATCH v4 5/8] phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver Richard Zhu
2021-10-29  8:12   ` Marcel Ziswiler
2021-10-29  8:45     ` Richard Zhu
2021-10-29 17:44       ` Tim Harvey
2021-11-01  8:19         ` Richard Zhu
2021-11-01 17:13           ` Tim Harvey
2021-11-01 23:52             ` Marcel Ziswiler
2021-11-02  2:41               ` Richard Zhu
2021-10-28  7:27 ` [PATCH v4 6/8] arm64: dts: imx8mm: Add the pcie support Richard Zhu
2021-10-28  7:27 ` [PATCH v4 7/8] arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board Richard Zhu
2021-10-29  8:21   ` Marcel Ziswiler
2021-10-29  8:46     ` Richard Zhu
2021-10-28  7:27 ` [PATCH v4 8/8] PCI: imx: Add the imx8mm pcie support Richard Zhu
2021-10-28 18:17 ` [PATCH v4 0/8] add the imx8m pcie phy driver and " Tim Harvey
2021-10-29  1:11   ` Richard Zhu

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