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From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, marcel.ziswiler@toradex.com,
tharvey@gateworks.com, kishon@ti.com, vkoul@kernel.org,
robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v4 6/8] arm64: dts: imx8mm: Add the pcie support
Date: Thu, 28 Oct 2021 15:27:15 +0800 [thread overview]
Message-ID: <1635406037-20900-7-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1635406037-20900-1-git-send-email-hongxing.zhu@nxp.com>
Add the PCIe support on i.MX8MM platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 33 ++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 0844f3144887..75f4317215ac 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -520,7 +520,7 @@ iomuxc: pinctrl@30330000 {
};
gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -1179,6 +1179,37 @@ gpmi: nand-controller@33002000{
status = "disabled";
};
+ pcie0: pcie@33800000 {
+ compatible = "fsl,imx8mm-pcie";
+ reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ linux,pci-domain = <0>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ status = "disabled";
+ };
+
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.25.1
next prev parent reply other threads:[~2021-10-28 7:53 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 7:27 [PATCH v4 0/8] add the imx8m pcie phy driver and imx8mm " Richard Zhu
2021-10-28 7:27 ` [PATCH v4 1/8] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy Richard Zhu
2021-10-28 7:27 ` [PATCH v4 2/8] dt-bindings: phy: Add imx8 pcie phy driver support Richard Zhu
2021-10-28 7:27 ` [PATCH v4 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties Richard Zhu
2021-10-28 7:27 ` [PATCH v4 4/8] arm64: dts: imx8mm: Add the pcie phy support Richard Zhu
2021-10-28 7:27 ` [PATCH v4 5/8] phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver Richard Zhu
2021-10-29 8:12 ` Marcel Ziswiler
2021-10-29 8:45 ` Richard Zhu
2021-10-29 17:44 ` Tim Harvey
2021-11-01 8:19 ` Richard Zhu
2021-11-01 17:13 ` Tim Harvey
2021-11-01 23:52 ` Marcel Ziswiler
2021-11-02 2:41 ` Richard Zhu
2021-10-28 7:27 ` Richard Zhu [this message]
2021-10-28 7:27 ` [PATCH v4 7/8] arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board Richard Zhu
2021-10-29 8:21 ` Marcel Ziswiler
2021-10-29 8:46 ` Richard Zhu
2021-10-28 7:27 ` [PATCH v4 8/8] PCI: imx: Add the imx8mm pcie support Richard Zhu
2021-10-28 18:17 ` [PATCH v4 0/8] add the imx8m pcie phy driver and " Tim Harvey
2021-10-29 1:11 ` Richard Zhu
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