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* [PATCH 0/2] Add UART driver for Suplus SP7021 SoC
@ 2021-11-01  7:48 hammer.hsieh
  2021-11-01  7:48 ` [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver hammer.hsieh
                   ` (3 more replies)
  0 siblings, 4 replies; 19+ messages in thread
From: hammer.hsieh @ 2021-11-01  7:48 UTC (permalink / raw)
  To: gregkh, linux-serial, devicetree, linux-kernel, jirislaby, p.zabel
  Cc: tony.huang, wells.lu, hammer.hsieh

This is a patch series for UART driver for Suplus SP7021 SoC.

Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates
many peripherals (ex: UART. I2C, SPI, SDIO, eMMC, USB, SD card and
etc.) into a single chip. It is designed for industrial control.

Refer to:
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
https://tibbo.com/store/plus1.html

hammer.hsieh (2):
  dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  serial:sunplus-uart:Add Sunplus SoC UART Driver

 .../devicetree/bindings/serial/sunplus,uart.yaml   |  116 ++
 MAINTAINERS                                        |    7 +
 drivers/tty/serial/Kconfig                         |   23 +
 drivers/tty/serial/Makefile                        |    1 +
 drivers/tty/serial/sunplus-uart.c                  | 1848 ++++++++++++++++++++
 include/soc/sunplus/sp_uart.h                      |  158 ++
 6 files changed, 2153 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,uart.yaml
 create mode 100644 drivers/tty/serial/sunplus-uart.c
 create mode 100644 include/soc/sunplus/sp_uart.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  2021-11-01  7:48 [PATCH 0/2] Add UART driver for Suplus SP7021 SoC hammer.hsieh
@ 2021-11-01  7:48 ` hammer.hsieh
  2021-11-01 13:20   ` Rob Herring
  2021-11-01 19:34   ` Rob Herring
  2021-11-01  7:48 ` [PATCH 2/2] serial:sunplus-uart:Add " hammer.hsieh
                   ` (2 subsequent siblings)
  3 siblings, 2 replies; 19+ messages in thread
From: hammer.hsieh @ 2021-11-01  7:48 UTC (permalink / raw)
  To: gregkh, linux-serial, devicetree, linux-kernel, jirislaby, p.zabel
  Cc: tony.huang, wells.lu, hammer.hsieh

Add bindings doc for Sunplus SoC UART Driver

Signed-off-by: hammer.hsieh <hammer.hsieh@sunplus.com>
---
 .../devicetree/bindings/serial/sunplus,uart.yaml   | 116 +++++++++++++++++++++
 MAINTAINERS                                        |   5 +
 2 files changed, 121 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,uart.yaml

diff --git a/Documentation/devicetree/bindings/serial/sunplus,uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,uart.yaml
new file mode 100644
index 0000000..f2ca9ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/sunplus,uart.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/sunplus,uart.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Sunplus SoC UART Controller Device Tree Bindings
+
+maintainers:
+  - Tony Huang <tony.huang@sunplus.com>
+  - Hammer Hsieh <hammer.hsieh@sunplus.com>
+  - Wells Lu <wells.lu@sunplus.com>
+
+allOf:
+  - $ref: serial.yaml#
+
+properties:
+  compatible:
+    const: sunplus,sp7021-uart
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    oneOf:
+      - items:
+        - const: UADMA
+        - const: PERI0
+      - items:
+        - const: UADMA
+        - const: PERI1
+      - items:
+        - const: HWUA
+        - const: PERI0
+      - items:
+        - const: HWUA
+        - const: PERI1
+
+  resets:
+    maxItems: 1
+
+  which-uart:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 1, 2, 3, 4]
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/sp-sp7021.h>
+    #include <dt-bindings/reset/sp-sp7021.h>
+    aliases {
+            serial0 = &uart0;
+            serial1 = &uart1;
+            serial10 = &uartdmarx0;
+            serial20 = &uartdmatx0;
+    };
+
+    uart0: serial@9c000900 {
+      compatible = "sunplus,sp7021-uart";
+      reg = <0x9c000900 0x80>;
+      interrupt-parent = <&intc>;
+      interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&clkc UA0>;
+      resets = <&rstc RST_UA0>;
+    };
+
+    // UART1 PIO mode
+    uart1: serial@9c000980 {
+        compatible = "sunplus,sp7021-uart";
+        reg = <0x9c000980 0x80>;
+        interrupt-parent = <&intc>;
+        interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc UA1>;
+        resets = <&rstc RST_UA1>;
+    };
+
+    // UART1 DMA mode for RX
+    uartdmarx0: serial@9c008980 {
+        compatible = "sunplus,sp7021-uart";
+        reg = <0x9c008980 0x40>;
+        interrupt-parent = <&intc>;
+        interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc UADMA>, <&clkc PERI0>;
+        clock-names = "UADMA", "PERI0";
+        resets = <&rstc RST_UADMA>;
+        which-uart = <1>;
+    };
+
+    // UART1 DMA mode for TX
+    uartdmatx0: serial@9c008a00 {
+        compatible = "sunplus,sp7021-uart";
+        reg = <0x9c008a00 0x40>, <0x9c008880 0x80>;
+        clocks = <&clkc HWUA>, <&clkc PERI0>;
+        clock-names = "HWUA", "PERI0";
+        resets = <&rstc RST_HWUA>;
+        which-uart = <1>;
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 3b79fd4..f863e97 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17945,6 +17945,11 @@ L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/ethernet/dlink/sundance.c
 
+SUNPLUS UART DRIVER
+M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/serial/sunplus,uart.yaml
+
 SUPERH
 M:	Yoshinori Sato <ysato@users.sourceforge.jp>
 M:	Rich Felker <dalias@libc.org>
-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-01  7:48 [PATCH 0/2] Add UART driver for Suplus SP7021 SoC hammer.hsieh
  2021-11-01  7:48 ` [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver hammer.hsieh
@ 2021-11-01  7:48 ` hammer.hsieh
  2021-11-01  7:56   ` Greg KH
  2021-11-10  7:51 ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Hammer Hsieh
  2021-11-19  5:19 ` [PATCH v3 " Hammer Hsieh
  3 siblings, 1 reply; 19+ messages in thread
From: hammer.hsieh @ 2021-11-01  7:48 UTC (permalink / raw)
  To: gregkh, linux-serial, devicetree, linux-kernel, jirislaby, p.zabel
  Cc: tony.huang, wells.lu, hammer.hsieh

Add Sunplus SoC UART Driver

Signed-off-by: hammer.hsieh <hammer.hsieh@sunplus.com>
---
 MAINTAINERS                       |    2 +
 drivers/tty/serial/Kconfig        |   23 +
 drivers/tty/serial/Makefile       |    1 +
 drivers/tty/serial/sunplus-uart.c | 1848 +++++++++++++++++++++++++++++++++++++
 include/soc/sunplus/sp_uart.h     |  158 ++++
 5 files changed, 2032 insertions(+)
 create mode 100644 drivers/tty/serial/sunplus-uart.c
 create mode 100644 include/soc/sunplus/sp_uart.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f863e97..0176026 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17949,6 +17949,8 @@ SUNPLUS UART DRIVER
 M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/serial/sunplus,uart.yaml
+F:	drivers/tty/serial/sunplus-uart.c
+F:	include/soc/sunplus/sp-uart.h
 
 SUPERH
 M:	Yoshinori Sato <ysato@users.sourceforge.jp>
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 131a6a5..319f5db 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1561,6 +1561,29 @@ config SERIAL_LITEUART_CONSOLE
 	  and warnings and which allows logins in single user mode).
 	  Otherwise, say 'N'.
 
+config SERIAL_SUNPLUS
+	bool "Sunplus UART support"
+	depends on OF
+	select SERIAL_CORE
+	help
+	  Select this option if you would like to use Sunplus serial port on
+	  Sunplus SoC SP7021.
+	  If you enable this option, Sunplus serial ports in the system will
+	  be registered as ttySx.
+
+config SERIAL_SUNPLUS_CONSOLE
+	bool "Console on Sunplus UART"
+	depends on SERIAL_SUNPLUS
+	select SERIAL_CORE_CONSOLE
+	select SERIAL_EARLYCON
+	help
+	  Select this option if you would like to use a Sunplus UART as the
+	  system console.
+	  Even if you say Y here, the currently visible virtual console
+	  (/dev/tty0) will still be used as the system console by default, but
+	  you can alter that using a kernel command line option such as
+	  "console=ttySx".
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 7da0856..61cc8de 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_SERIAL_RDA)	+= rda-uart.o
 obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
 obj-$(CONFIG_SERIAL_SIFIVE)	+= sifive.o
 obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o
+obj-$(CONFIG_SERIAL_SUNPLUS)	+= sunplus-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)	+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/sunplus-uart.c b/drivers/tty/serial/sunplus-uart.c
new file mode 100644
index 0000000..d1524dc
--- /dev/null
+++ b/drivers/tty/serial/sunplus-uart.c
@@ -0,0 +1,1848 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Sunplus SoC UART driver
+ *
+ * Author: Hammer Hsieh <hammer.hsieh@sunplus.com>
+ * Tony Huang <tony.huang@sunplus.com>
+ * Wells Lu <wells.lu@sunplus.com>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/of_platform.h>
+#include <asm/irq.h>
+#if defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#include <linux/sysrq.h>
+#endif
+#include <linux/serial_core.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <soc/sunplus/sp_uart.h>
+
+#ifdef CONFIG_PM_RUNTIME_UART
+#include <linux/pm_runtime.h>
+#endif
+
+#include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <dt-bindings/clock/sp-sp7021.h>
+#include <dt-bindings/pinctrl/sppctl-sp7021.h>
+#include <linux/delay.h>
+#include <linux/hrtimer.h>
+
+#define DEVICE_NAME				"ttyS"
+#define SP_UART_MAJOR			TTY_MAJOR
+#define SP_UART_MINOR_START		64
+
+#define NUM_UART		6	/* serial0,  ... */
+#define NUM_UARTDMARX	2	/* serial10, ... */
+#define NUM_UARTDMATX	2	/* serial20, ... */
+
+#define ID_BASE_DMARX	10
+#define ID_BASE_DMATX	20
+
+#define IS_UARTDMARX_ID(X) \
+	(((X) >= (ID_BASE_DMARX)) && ((X) < (ID_BASE_DMARX + NUM_UARTDMARX)))
+#define IS_UARTDMATX_ID(X) \
+	(((X) >= (ID_BASE_DMATX)) && ((X) < (ID_BASE_DMATX + NUM_UARTDMATX)))
+
+//#define TTYS_KDBG_INFO
+#define TTYS_KDBG_ERR
+//#define TTYS_GPIO
+
+#ifdef TTYS_KDBG_INFO
+#define DBG_INFO(fmt, args ...)	pr_info("K_TTYS: " fmt, ## args)
+#else
+#define DBG_INFO(fmt, args ...)
+#endif
+#ifdef TTYS_KDBG_ERR
+#define DBG_ERR(fmt, args ...)	pr_err("K_TTYS: " fmt, ## args)
+#else
+#define DBG_ERR(fmt, args ...)
+#endif
+
+#define SP_UART_CREAD_DISABLED		(1 << 16)
+
+#define UARXDMA_BUF_SZ			PAGE_SIZE
+#define MAX_SZ_RXDMA_ISR		(1 << 9)
+#define UATXDMA_BUF_SZ			PAGE_SIZE
+
+#define CLK_HIGH_UART			202500000
+#define UART_RATIO				232
+
+#if defined(CONFIG_SP_MON)
+extern unsigned int uart0_mask_tx;	/* Used for masking uart0 tx output */
+#endif
+
+struct sunplus_uart_port {
+	char name[16];
+	struct uart_port uport;
+	struct sunplus_uartdma_info *uartdma_rx;
+	struct sunplus_uartdma_info *uartdma_tx;
+	struct clk *clk;
+	struct reset_control *rstc;
+	struct gpio_desc *rts_gpio;
+	struct hrtimer CheckTXE;
+	struct hrtimer DelayRtsBeforeSend;
+	struct hrtimer DelayRtsAfterSend;
+};
+struct sunplus_uart_port sunplus_uart_ports[NUM_UART];
+
+struct sunplus_uartdma_info {
+	void __iomem *membase;	/* virtual address */
+	unsigned long addr_phy;
+	void __iomem *gdma_membase;	/* virtual address */
+	int irq;
+	int which_uart;
+	struct sunplus_uart_port *binding_port;
+	void *buf_va;
+	dma_addr_t dma_handle;
+};
+static struct sunplus_uartdma_info
+	sunplus_uartdma[NUM_UARTDMARX + NUM_UARTDMATX];
+
+static inline void sp_uart_set_int_en(unsigned char __iomem *base,
+	unsigned int int_state)
+{
+	writel(int_state, &((struct regs_uart *)base)->uart_isc);
+}
+
+static inline unsigned int sp_uart_get_int_en(unsigned char __iomem *base)
+{
+	return readl(&((struct regs_uart *)base)->uart_isc);
+}
+
+static inline int sp_uart_get_char(unsigned char __iomem *base)
+{
+	return readl(&((struct regs_uart *)base)->uart_data);
+}
+
+static inline void sp_uart_put_char(struct uart_port *port, unsigned int ch)
+{
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	struct sunplus_uartdma_info *uartdma_tx =
+		sp_port->uartdma_tx;
+	struct regs_uatxdma *txdma_reg;
+	unsigned char __iomem *base = port->membase;
+	u32 addr_sw, addr_start;
+	u32 offset_sw;
+	u8 *byte_ptr;
+
+#if defined(CONFIG_SP_MON)
+	if ((uart0_mask_tx == 1) && ((u32)base == LOGI_ADDR_UART0_REG))
+		return;
+#endif
+
+	if (!uartdma_tx) {
+		writel(ch, &((struct regs_uart *)base)->uart_data);
+	} else {
+		txdma_reg = (struct regs_uatxdma *)(uartdma_tx->membase);
+		addr_sw = readl(&(txdma_reg->txdma_wr_adr));
+		addr_start = readl(&(txdma_reg->txdma_start_addr));
+		offset_sw = addr_sw - addr_start;
+		byte_ptr = (u8 *)(uartdma_tx->buf_va + offset_sw);
+		*byte_ptr = (u8)(ch);
+		if (offset_sw == (UATXDMA_BUF_SZ - 1))
+			writel((u32)(uartdma_tx->dma_handle), &(txdma_reg->txdma_wr_adr));
+		else
+			writel((addr_sw + 1), &(txdma_reg->txdma_wr_adr));
+	}
+}
+
+static inline unsigned int sp_uart_get_line_status(unsigned char __iomem *base)
+{
+	return readl(&((struct regs_uart *)base)->uart_lsr);
+}
+
+static inline u32 sp_uart_line_status_tx_buf_not_full(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	struct sunplus_uartdma_info *uartdma_tx =
+		sp_port->uartdma_tx;
+	struct regs_uatxdma *txdma_reg;
+	unsigned char __iomem *base = port->membase;
+	u32 addr_sw, addr_hw;
+
+	if (uartdma_tx) {
+		txdma_reg = (struct regs_uatxdma *)(uartdma_tx->membase);
+		if (readl(&(txdma_reg->txdma_status)) & 0x01)
+			return 0;
+
+		addr_sw = readl(&(txdma_reg->txdma_wr_adr));
+		addr_hw = readl(&(txdma_reg->txdma_rd_adr));
+		if (addr_sw >= addr_hw)
+			return (UATXDMA_BUF_SZ - (addr_sw - addr_hw));
+		else
+			return (addr_hw - addr_sw);
+
+	} else {
+		if (readl(&((struct regs_uart *)base)->uart_lsr) & SP_UART_LSR_TX) {
+			/*
+			 * In PIO mode, just return 1 byte
+			 * becauase exactly number is unknown
+			 */
+			return 1;
+		} else {
+			return 0;
+		}
+	}
+}
+
+static inline void sp_uart_set_line_ctrl(unsigned char __iomem *base,
+	unsigned int ctrl)
+{
+	writel(ctrl, &((struct regs_uart *)base)->uart_lcr);
+}
+
+static inline unsigned int sp_uart_get_line_ctrl(unsigned char __iomem *base)
+{
+	return readl(&((struct regs_uart *)base)->uart_lcr);
+}
+
+static inline void sp_uart_set_divider_low_register(unsigned char __iomem *base,
+	unsigned int val)
+{
+	writel(val, &((struct regs_uart *)base)->uart_div_l);
+}
+
+static inline unsigned int sp_uart_get_divider_low_register(unsigned char __iomem *base)
+{
+	return readl(&((struct regs_uart *)base)->uart_div_l);
+}
+
+static inline void sp_uart_set_divider_high_register(unsigned char __iomem *base,
+	unsigned int val)
+{
+	writel(val, &((struct regs_uart *)base)->uart_div_h);
+}
+
+static inline unsigned int sp_uart_get_divider_high_register(unsigned char __iomem *base)
+{
+	return readl(&((struct regs_uart *)base)->uart_div_h);
+}
+
+static inline void sp_uart_set_rx_residue(unsigned char __iomem *base,
+	unsigned int val)
+{
+	writel(val, &((struct regs_uart *)base)->uart_rx_residue);
+}
+
+static inline void sp_uart_set_modem_ctrl(unsigned char __iomem *base,
+	unsigned int val)
+{
+	writel(val, &((struct regs_uart *)base)->uart_mcr);
+}
+
+static inline unsigned int sp_uart_get_modem_ctrl(unsigned char __iomem *base)
+{
+	return readl(&((struct regs_uart *)base)->uart_mcr);
+}
+
+static inline void sp_uart_set_clk_src(unsigned char __iomem *base,
+	unsigned int val)
+{
+	writel(val, &((struct regs_uart *)base)->uart_clk_src);
+}
+
+/*
+ * Note:
+ * When (uart0_as_console == 0), please make sure:
+ *     There is no "console=ttyS0,115200", "earlyprintk", ... in kernel command line.
+ *     In /etc/inittab, there is no something like "ttyS0::respawn:/bin/sh"
+ */
+unsigned int uart0_as_console = ~0;
+unsigned int uart_enable_status = ~0;	/* bit 0: UART0, bit 1: UART1, ... */
+
+#if defined(CONFIG_SP_MON)
+extern int sysrqCheckState(char, struct uart_port *);
+#endif
+
+static struct sunplus_uartdma_info *sunplus_uartdma_rx_binding(int id)
+{
+	int i;
+
+	for (i = 0; i < NUM_UARTDMARX; i++) {
+		if ((sunplus_uartdma[i].which_uart == id) && (sunplus_uartdma[i].membase)) {
+			sunplus_uartdma[i].binding_port = &sunplus_uart_ports[id];
+			return &sunplus_uartdma[i];
+		}
+	}
+	return NULL;
+}
+
+static struct sunplus_uartdma_info *sunplus_uartdma_tx_binding(int id)
+{
+	int i;
+
+	for (i = NUM_UARTDMARX; i < (NUM_UARTDMARX + NUM_UARTDMATX); i++) {
+		if ((sunplus_uartdma[i].which_uart == id) && (sunplus_uartdma[i].membase)) {
+			sunplus_uartdma[i].binding_port = &sunplus_uart_ports[id];
+			return &sunplus_uartdma[i];
+		}
+	}
+	return NULL;
+}
+
+static inline void wait_for_xmitr(struct uart_port *port)
+{
+	while (1) {
+		if (sp_uart_line_status_tx_buf_not_full(port))
+			break;
+	}
+}
+
+static unsigned int sunplus_uart_ops_tx_empty(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = (struct sunplus_uart_port *)(port->private_data);
+	struct sunplus_uartdma_info *uartdma_tx = sp_port->uartdma_tx;
+	struct regs_uatxdma *txdma_reg;
+
+	if (uartdma_tx) {
+		txdma_reg = (struct regs_uatxdma *)(uartdma_tx->membase);
+		if (readl(&(txdma_reg->txdma_status)) & 0x02)
+			return TIOCSER_TEMT;
+		else
+			return 0;
+	} else {
+		return ((sp_uart_get_line_status(port->membase) & SP_UART_LSR_TXE)
+			? TIOCSER_TEMT : 0);
+	}
+}
+
+static void sunplus_uart_ops_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	unsigned char mcr = sp_uart_get_modem_ctrl(port->membase);
+	ktime_t ktime;
+
+	if (mctrl & TIOCM_DTR)
+		mcr |= SP_UART_MCR_DTS;
+	else
+		mcr &= ~SP_UART_MCR_DTS;
+
+	if (mctrl & TIOCM_RTS) {
+		if ((sp_port->uport.rs485.flags & SER_RS485_ENABLED)
+			&& (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND))
+			mcr &= ~SP_UART_MCR_RTS;  /* RTS invert */
+		else
+			mcr |= SP_UART_MCR_RTS;
+	} else {
+		/* data transfer ended */
+		if (sp_port->uport.rs485.flags & SER_RS485_ENABLED)
+			return;
+
+		mcr &= ~SP_UART_MCR_RTS;
+	}
+
+	if (mctrl & TIOCM_CAR)
+		mcr |= SP_UART_MCR_DCD;
+	else
+		mcr &= ~SP_UART_MCR_DCD;
+
+	if (mctrl & TIOCM_RI)
+		mcr |= SP_UART_MCR_RI;
+	else
+		mcr &= ~SP_UART_MCR_RI;
+
+	if (mctrl & TIOCM_LOOP)
+		mcr |= SP_UART_MCR_LB;
+	else
+		mcr &= ~SP_UART_MCR_LB;
+
+	sp_uart_set_modem_ctrl(port->membase, mcr);
+
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED) {
+		mcr = sp_uart_get_modem_ctrl(port->membase);
+		if (mctrl & TIOCM_RTS) {
+			if (((mcr & SP_UART_MCR_RTS)
+				&& (sp_port->uport.rs485.flags & SER_RS485_RTS_AFTER_SEND))
+				|| (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND)) {
+				if (!IS_ERR(sp_port->rts_gpio))
+					gpiod_set_value(sp_port->rts_gpio, 1);
+				dev_dbg(port->dev, "%s set rts_gpio=1\n", port->name);
+				if (sp_port->uport.rs485.delay_rts_before_send == 0) {
+					ktime = ktime_set(0, 500000); /* 500us */
+					hrtimer_start(&sp_port->CheckTXE, ktime, HRTIMER_MODE_REL);
+				}
+			}
+		}
+	}
+}
+
+static unsigned int sunplus_uart_ops_get_mctrl(struct uart_port *port)
+{
+	unsigned char status;
+	unsigned int ret = 0;
+
+	status = sp_uart_get_modem_ctrl(port->membase);
+
+	if (status & SP_UART_MCR_DTS)
+		ret |= TIOCM_DTR;
+
+	if (status & SP_UART_MCR_RTS)
+		ret |= TIOCM_RTS;
+
+	if (status & SP_UART_MCR_DCD)
+		ret |= TIOCM_CAR;
+
+	if (status & SP_UART_MCR_RI)
+		ret |= TIOCM_RI;
+
+	if (status & SP_UART_MCR_LB)
+		ret |= TIOCM_LOOP;
+
+	if (status & SP_UART_MCR_AC)
+		ret |= TIOCM_CTS;
+
+	return ret;
+}
+
+static void sunplus_uart_ops_stop_tx(struct uart_port *port)
+{
+	unsigned int isc = sp_uart_get_int_en(port->membase);
+
+	/*
+	 * Even if (uartdma_tx != NULL), "BUF_NOT_FULL" interrupt
+	 * is used for getting into ISR
+	 */
+	isc &= ~SP_UART_ISC_TXM;
+	sp_uart_set_int_en(port->membase, isc);
+}
+
+static inline void __start_tx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = sp_uart_get_int_en(port->membase) | SP_UART_ISC_TXM;
+	sp_uart_set_int_en(port->membase, isc);
+}
+
+static void sunplus_uart_ops_start_tx(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	ktime_t ktime;
+	int val;
+
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED) {
+		val = (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND ? 1 : 0);
+		if (!IS_ERR(sp_port->rts_gpio))
+			gpiod_set_value(sp_port->rts_gpio, val);
+
+		dev_dbg(port->dev, "%s set rts_gpio=%d\n", sp_port->uport.name, val);
+		if (sp_port->uport.rs485.delay_rts_before_send > 0) {
+			long nsec = sp_port->uport.rs485.delay_rts_before_send * 1000000;
+
+			ktime = ktime_set(0, nsec);
+			hrtimer_start(&sp_port->DelayRtsBeforeSend, ktime, HRTIMER_MODE_REL);
+			return;
+		}
+	}
+	__start_tx(port);
+}
+
+static void sunplus_uart_ops_stop_rx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = sp_uart_get_int_en(port->membase);
+	isc &= ~SP_UART_ISC_RXM;
+	sp_uart_set_int_en(port->membase, isc);
+}
+
+static void sunplus_uart_ops_enable_ms(struct uart_port *port)
+{
+	/* Do nothing */
+}
+
+static void sunplus_uart_ops_break_ctl(struct uart_port *port, int ctl)
+{
+	unsigned long flags;
+	unsigned int h_lcr;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	h_lcr = sp_uart_get_line_ctrl(port->membase);
+	if (ctl != 0)
+		h_lcr |= SP_UART_LCR_BC;	/* start break */
+	else
+		h_lcr &= ~SP_UART_LCR_BC;	/* stop break */
+
+	sp_uart_set_line_ctrl(port->membase, h_lcr);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void transmit_chars(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	struct sunplus_uartdma_info *uartdma_tx = sp_port->uartdma_tx;
+	u32 tx_buf_available;
+	struct regs_uatxdma *txdma_reg;
+	u32 addr_sw, addr_start;
+	u32 offset_sw;
+	u8 *byte_ptr;
+	struct circ_buf *xmit = &port->state->xmit;
+
+	if (port->x_char) {
+		sp_uart_put_char(port, port->x_char);
+		port->icount.tx++;
+		port->x_char = 0;
+		return;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+		sunplus_uart_ops_stop_tx(port);
+		return;
+	}
+
+	if (uartdma_tx) {
+		txdma_reg = (struct regs_uatxdma *)(uartdma_tx->membase);
+		addr_sw = readl(&(txdma_reg->txdma_wr_adr));
+		addr_start = readl(&(txdma_reg->txdma_start_addr));
+		offset_sw = addr_sw - addr_start;
+		byte_ptr = (u8 *)(uartdma_tx->buf_va + offset_sw);
+		tx_buf_available = sp_uart_line_status_tx_buf_not_full(port);
+		while (tx_buf_available) {
+			*byte_ptr = xmit->buf[xmit->tail];
+			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+			port->icount.tx++;
+
+			byte_ptr++;
+			addr_sw++;
+			offset_sw++;
+			tx_buf_available--;
+			if (offset_sw == UATXDMA_BUF_SZ) {
+				offset_sw = 0;
+				addr_sw = (u32)(uartdma_tx->dma_handle);
+				byte_ptr = (u8 *)(uartdma_tx->buf_va);
+			}
+
+			if (uart_circ_empty(xmit))
+				break;
+		}
+		writel(addr_sw, &(txdma_reg->txdma_wr_adr));
+	} else {
+		do {
+			sp_uart_put_char(port, xmit->buf[xmit->tail]);
+			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+			port->icount.tx++;
+
+			if (uart_circ_empty(xmit))
+				break;
+		} while (sp_uart_line_status_tx_buf_not_full(port));
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (uart_circ_empty(xmit))
+		sunplus_uart_ops_stop_tx(port);
+}
+
+/* called by ISR */
+static void receive_chars(struct uart_port *port)
+{
+	struct tty_struct *tty = port->state->port.tty;
+	unsigned char lsr = sp_uart_get_line_status(port->membase);
+	unsigned int ch, flag;
+
+	do {
+		ch = sp_uart_get_char(port->membase);
+
+#if defined(CONFIG_SP_MON)
+		if (sysrqCheckState(ch, port) != 0)
+			goto ignore_char;
+#endif
+
+		flag = TTY_NORMAL;
+		port->icount.rx++;
+
+		if (unlikely(lsr & SP_UART_LSR_BRK_ERROR_BITS)) {
+			if (port->cons == NULL)
+				DBG_ERR("UART%d, SP_UART_LSR_BRK_ERROR_BITS, lsr = 0x%08X\n",
+					port->line, lsr);
+
+			if (lsr & SP_UART_LSR_BC) {
+				lsr &= ~(SP_UART_LSR_FE | SP_UART_LSR_PE);
+				port->icount.brk++;
+				if (uart_handle_break(port))
+					goto ignore_char;
+			} else if (lsr & SP_UART_LSR_PE) {
+				if (port->cons == NULL)
+					DBG_ERR("UART%d, SP_UART_LSR_PE\n", port->line);
+				port->icount.parity++;
+			} else if (lsr & SP_UART_LSR_FE) {
+				if (port->cons == NULL)
+					DBG_ERR("UART%d, SP_UART_LSR_FE\n", port->line);
+				port->icount.frame++;
+			}
+			if (lsr & SP_UART_LSR_OE) {
+				if (port->cons == NULL)
+					DBG_ERR("UART%d, SP_UART_LSR_OE\n", port->line);
+				port->icount.overrun++;
+			}
+
+			/*
+			 * Mask off conditions which should be ignored.
+			 */
+
+			/* lsr &= port->read_status_mask; */
+
+			if (lsr & SP_UART_LSR_BC)
+				flag = TTY_BREAK;
+			else if (lsr & SP_UART_LSR_PE)
+				flag = TTY_PARITY;
+			else if (lsr & SP_UART_LSR_FE)
+				flag = TTY_FRAME;
+		}
+
+		if (port->ignore_status_mask & SP_UART_CREAD_DISABLED)
+			goto ignore_char;
+
+		if (uart_handle_sysrq_char(port, ch))
+			goto ignore_char;
+
+		uart_insert_char(port, lsr, SP_UART_LSR_OE, ch, flag);
+
+ignore_char:
+		lsr = sp_uart_get_line_status(port->membase);
+	} while (lsr & SP_UART_LSR_RX);
+
+	if (tty) {
+		spin_unlock(&port->lock);
+		tty_flip_buffer_push(tty->port);
+		spin_lock(&port->lock);
+	}
+}
+
+static irqreturn_t sunplus_uart_irq(int irq, void *args)
+{
+	struct uart_port *port = (struct uart_port *)args;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	if (sp_uart_get_int_en(port->membase) & SP_UART_ISC_RX)
+		receive_chars(port);
+
+	if (sp_uart_get_int_en(port->membase) & SP_UART_ISC_TX)
+		transmit_chars(port);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+/* called by ISR */
+static void receive_chars_rxdma(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	struct sunplus_uartdma_info *uartdma_rx;
+	struct regs_uarxdma *rxdma_reg;
+	struct tty_struct *tty = port->state->port.tty;
+	u32 offset_sw, offset_hw, rx_size, dma_start;
+	u8 *sw_ptr, *buf_end_ptr, *u8_ptr;
+	u32 icount_rx;
+	u32 tmp_u32;
+	u8 tmp_buf[32];
+	int i;
+
+	uartdma_rx = sp_port->uartdma_rx;
+	rxdma_reg = (struct regs_uarxdma *)(uartdma_rx->membase);
+
+	dma_start = readl(&(rxdma_reg->rxdma_start_addr));
+	offset_sw = readl(&(rxdma_reg->rxdma_rd_adr)) - dma_start;
+	offset_hw = readl(&(rxdma_reg->rxdma_wr_adr)) - dma_start;
+
+	if (offset_hw >= offset_sw)
+		rx_size = offset_hw - offset_sw;
+	else
+		rx_size = offset_hw + UARXDMA_BUF_SZ - offset_sw;
+
+	sw_ptr = (u8 *)(uartdma_rx->buf_va + offset_sw);
+	buf_end_ptr = (u8 *)(uartdma_rx->buf_va + UARXDMA_BUF_SZ);
+
+	/*
+	 * Retrieve all data in ISR.
+	 * The max. received size is (buffer_size - threshold_size)
+	 * = (rxdma_length_thr[31:16] - rxdma_length_thr[15:0]) = MAX_SZ_RXDMA_ISR
+	 * In order to limit the execution time in this ISR:
+	 * => Increase rxdma_length_thr[15:0] to shorten each ISR execution time.
+	 * => Don't need to set a small threshold_size,
+	 *    and split a long ISR into several shorter ISRs.
+	 */
+	icount_rx = 0;
+	while (rx_size > icount_rx) {
+		/* 32-byte aligned */
+		if (!(((unsigned long)(sw_ptr)) & (32 - 1))
+		    && ((rx_size - icount_rx) >= 32)) {
+			/*
+			 * Copy 32 bytes data from non cache area to cache area.
+			 * => It should use less DRAM controller's read command.
+			 */
+			memcpy(tmp_buf, sw_ptr, 32);
+			u8_ptr = (u8 *)(tmp_buf);
+			for (i = 0; i < 32; i++) {
+				port->icount.rx++;
+				uart_insert_char(port, 0, SP_UART_LSR_OE,
+					(unsigned int)(*u8_ptr), TTY_NORMAL);
+				u8_ptr++;
+			}
+			sw_ptr += 32;
+			icount_rx += 32;
+		} else {
+			port->icount.rx++;
+			uart_insert_char(port, 0, SP_UART_LSR_OE,
+				(unsigned int)(*sw_ptr), TTY_NORMAL);
+			sw_ptr++;
+			icount_rx++;
+		}
+		if (sw_ptr >= buf_end_ptr)
+			sw_ptr = (u8 *)(uartdma_rx->buf_va);
+	}
+	tmp_u32 = readl(&(rxdma_reg->rxdma_rd_adr)) + rx_size;
+	if (tmp_u32 <= readl(&(rxdma_reg->rxdma_end_addr)))
+		writel(tmp_u32, &(rxdma_reg->rxdma_rd_adr));
+	else
+		writel((tmp_u32 - UARXDMA_BUF_SZ), &(rxdma_reg->rxdma_rd_adr));
+
+	spin_unlock(&port->lock);
+	tty_flip_buffer_push(tty->port);
+	spin_lock(&port->lock);
+
+	writel(readl(&(rxdma_reg->rxdma_enable_sel)) | DMA_INT,
+		&(rxdma_reg->rxdma_enable_sel));
+	writel(readl(&(rxdma_reg->rxdma_enable_sel)) | DMA_GO,
+		&(rxdma_reg->rxdma_enable_sel));
+}
+
+static irqreturn_t sunplus_uart_rxdma_irq(int irq, void *args)
+{
+	struct uart_port *port = (struct uart_port *)args;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+#ifdef TTYS_GPIO
+	gpio_set_value(0, 1);
+#endif
+	receive_chars_rxdma(port);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int sunplus_uart_ops_startup(struct uart_port *port)
+{
+	int ret;
+	u32 timeout, interrupt_en;
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	struct sunplus_uartdma_info *uartdma_rx, *uartdma_tx;
+	struct regs_uarxdma *rxdma_reg;
+	struct regs_uatxdma *txdma_reg;
+	struct regs_uatxgdma *gdma_reg;
+	unsigned int ch;
+
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED)
+		hrtimer_cancel(&sp_port->DelayRtsAfterSend);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (port->line > 0) {
+		ret = pm_runtime_get_sync(port->dev);
+		if (ret < 0)
+			goto out;
+	}
+#endif
+
+	ret = request_irq(port->irq, sunplus_uart_irq, 0, sp_port->name, port);
+	if (ret)
+		return ret;
+
+	uartdma_rx = sp_port->uartdma_rx;
+	if (uartdma_rx) {
+		rxdma_reg = (struct regs_uarxdma *)(uartdma_rx->membase);
+
+		if (uartdma_rx->buf_va == NULL) {
+			/* Drop data in Rx FIFO (PIO mode) */
+			while (sp_uart_get_line_status(port->membase) & SP_UART_LSR_RX)
+				ch = sp_uart_get_char(port->membase);
+
+			uartdma_rx->buf_va =
+				dma_alloc_coherent(port->dev, UARXDMA_BUF_SZ,
+				&(uartdma_rx->dma_handle), GFP_KERNEL);
+			if (uartdma_rx->buf_va == NULL) {
+				DBG_ERR("%s, %d, Can't allocation buffer for %s\n",
+					__func__, __LINE__, sp_port->name);
+				ret = -ENOMEM;
+				goto error_01;
+			}
+			DBG_INFO("DMA buffer (Rx) for %s: VA: 0x%p, PA: 0x%x\n",
+				sp_port->name, uartdma_rx->buf_va, (u32)(uartdma_rx->dma_handle));
+
+			writel((u32)(uartdma_rx->dma_handle), &(rxdma_reg->rxdma_start_addr));
+			writel((u32)(uartdma_rx->dma_handle), &(rxdma_reg->rxdma_rd_adr));
+
+			/* Force to use CLK_HIGH_UART in this mode */
+			/* Switch clock source when setting baud rate */
+			timeout = (CLK_HIGH_UART / 2) / 1000000 * 1000;	/* 1 msec */
+
+			/* DBG_INFO("timeout: 0x%x\n", timeout); */
+			writel(timeout, &(rxdma_reg->rxdma_timeout_set));
+
+			/*
+			 * When there are only rxdma_length_thr[15:0] bytes
+			 * of free buffer => Trigger interrupt
+			 */
+			writel(((UARXDMA_BUF_SZ << 16) | (UARXDMA_BUF_SZ - MAX_SZ_RXDMA_ISR)),
+			    &(rxdma_reg->rxdma_length_thr));
+			writel((readl(&(rxdma_reg->rxdma_enable_sel)) & (~DMA_SEL_UARTX_MASK)),
+			    &(rxdma_reg->rxdma_enable_sel));
+			writel((readl(&(rxdma_reg->rxdma_enable_sel))
+				| (DMA_INIT | (uartdma_rx->which_uart << DMA_SEL_UARTX_SHIFT))),
+				&(rxdma_reg->rxdma_enable_sel));
+			writel((readl(&(rxdma_reg->rxdma_enable_sel)) & (~DMA_INIT)),
+			    &(rxdma_reg->rxdma_enable_sel));
+			writel((readl(&(rxdma_reg->rxdma_enable_sel))
+				| (DMA_SW_RST_B | DMA_AUTO_ENABLE
+				| DMA_TIMEOUT_INT_EN | DMA_ENABLE)),
+				&(rxdma_reg->rxdma_enable_sel));
+			writel((readl(&(rxdma_reg->rxdma_enable_sel)) | (DMA_GO)),
+			    &(rxdma_reg->rxdma_enable_sel));
+		}
+		DBG_INFO("Enable RXDMA for %s (irq=%d)\n", sp_port->name, uartdma_rx->irq);
+		ret = request_irq(uartdma_rx->irq, sunplus_uart_rxdma_irq, 0, "UARTDMA_RX", port);
+		if (ret) {
+			dma_free_coherent(port->dev, UARXDMA_BUF_SZ,
+				uartdma_rx->buf_va, uartdma_rx->dma_handle);
+			goto error_00;
+		}
+	}
+
+	uartdma_tx = sp_port->uartdma_tx;
+	if (uartdma_tx) {
+		txdma_reg = (struct regs_uatxdma *)(uartdma_tx->membase);
+		gdma_reg = (struct regs_uatxgdma *)(uartdma_tx->gdma_membase);
+		DBG_INFO("Enable TXDMA for %s\n", sp_port->name);
+
+		if (uartdma_tx->buf_va == NULL) {
+			uartdma_tx->buf_va =
+				dma_alloc_coherent(port->dev, UATXDMA_BUF_SZ,
+				&(uartdma_tx->dma_handle), GFP_KERNEL);
+			if (uartdma_tx->buf_va == NULL) {
+				DBG_ERR("%s, %d, Can't allocation buffer for %s\n",
+					__func__, __LINE__, sp_port->name);
+				ret = -ENOMEM;
+				goto error_01;
+			}
+			DBG_INFO("DMA buffer (Tx) for %s: VA: 0x%p, PA: 0x%x\n",
+				sp_port->name, uartdma_tx->buf_va, (u32)(uartdma_tx->dma_handle));
+
+			/*
+			 * set 1ms , set wr_adr , set start_addr/end_addr ,
+			 * set bind to uart# , set int enable ,
+			 * set txdma enable (Use ring buffer for UART's Tx)
+			 */
+			writel((CLK_HIGH_UART / 1000), &(txdma_reg->txdma_tmr_unit));
+			writel((u32)(uartdma_tx->dma_handle), &(txdma_reg->txdma_wr_adr));
+			writel((u32)(uartdma_tx->dma_handle), &(txdma_reg->txdma_start_addr));
+			writel(((u32)(uartdma_tx->dma_handle) + UATXDMA_BUF_SZ - 1),
+				&(txdma_reg->txdma_end_addr));
+			writel(uartdma_tx->which_uart, &(txdma_reg->txdma_sel));
+			writel(0x41, &(gdma_reg->gdma_int_en));
+			writel(0x00000005, &(txdma_reg->txdma_enable));
+		}
+	}
+
+	/*
+	 * don't need to use spin_lock_irqsave() because interrupts
+	 * are globally disabled
+	 */
+	spin_lock_irq(&port->lock);
+
+	/* SP_UART_ISC_TXM is enabled in .start_tx() */
+	interrupt_en = 0;
+	if (uartdma_rx == NULL)
+		interrupt_en |= SP_UART_ISC_RXM;
+
+	sp_uart_set_int_en(port->membase, interrupt_en);
+
+	spin_unlock_irq(&port->lock);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (port->line > 0)
+		pm_runtime_put(port->dev);
+
+	return 0;
+
+out:
+	if (port->line > 0) {
+		pr_info("pm_out\n");
+		pm_runtime_mark_last_busy(port->dev);
+		pm_runtime_put_autosuspend(port->dev);
+	}
+#endif
+	return 0;
+
+error_01:
+	if (uartdma_rx) {
+		dma_free_coherent(port->dev, UARXDMA_BUF_SZ,
+			uartdma_rx->buf_va, uartdma_rx->dma_handle);
+		free_irq(uartdma_rx->irq, port);
+	}
+error_00:
+	free_irq(port->irq, port);
+	return ret;
+}
+
+static void sunplus_uart_ops_shutdown(struct uart_port *port)
+{
+	unsigned long flags;
+	struct sunplus_uart_port *sp_port =
+		(struct sunplus_uart_port *)(port->private_data);
+	struct sunplus_uartdma_info *uartdma_rx;
+	struct regs_uarxdma *rxdma_reg;
+
+	spin_lock_irqsave(&port->lock, flags);
+	sp_uart_set_int_en(port->membase, 0);
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	free_irq(port->irq, port);
+
+	uartdma_rx = sp_port->uartdma_rx;
+	if (uartdma_rx) {
+		rxdma_reg = (struct regs_uarxdma *)(uartdma_rx->membase);
+
+		/* Drop whatever is still in buffer */
+		writel(readl(&(rxdma_reg->rxdma_wr_adr)), &(rxdma_reg->rxdma_rd_adr));
+
+		free_irq(uartdma_rx->irq, port);
+		DBG_INFO("free_irq(%d)\n", uartdma_rx->irq);
+	}
+
+	/* Disable flow control of Tx, so that queued data can be sent out
+	 * There is no way for s/w to let h/w abort in the middle of
+	 * transaction.
+	 * Don't reset module except it's in idle state. Otherwise, it might
+	 * cause bus to hang.
+	 */
+	sp_uart_set_modem_ctrl(port->membase,
+		sp_uart_get_modem_ctrl(port->membase) & (~(SP_UART_MCR_AC)));
+
+}
+
+static void sunplus_uart_ops_set_termios(struct uart_port *port,
+	struct ktermios *termios, struct ktermios *oldtermios)
+{
+	u32 clk, ext, div, div_l, div_h, baud;
+	u32 lcr;
+	unsigned long flags;
+
+	baud = uart_get_baud_rate(port, termios, oldtermios, 0, (CLK_HIGH_UART >> 4));
+
+	clk = port->uartclk;
+
+	/*
+	 * Send all data in Tx FIFO before changing clock source,
+	 * it should be UART0 only
+	 */
+	while (!(sp_uart_get_line_status(port->membase) & SP_UART_LSR_TXE))
+		;
+
+	/* Switch clock source: 0 for sysclk, 1 for XTAL */
+	sp_uart_set_clk_src(port->membase, clk == XTAL);
+
+	clk += baud >> 1;
+	div = clk / baud;
+	ext = div & 0x0F;
+	div = (div >> 4) - 1;
+	div_l = (div & 0xFF) | (ext << 12);
+	div_h = div >> 8;
+
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		lcr = SP_UART_LCR_WL5;
+		break;
+	case CS6:
+		lcr = SP_UART_LCR_WL6;
+		break;
+	case CS7:
+		lcr = SP_UART_LCR_WL7;
+		break;
+	default:	/* CS8 */
+		lcr = SP_UART_LCR_WL8;
+		break;
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		lcr |= SP_UART_LCR_ST;
+
+	if (termios->c_cflag & PARENB) {
+		lcr |= SP_UART_LCR_PE;
+
+		if (!(termios->c_cflag & PARODD))
+			lcr |= SP_UART_LCR_PR;
+	}
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	port->read_status_mask = 0;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= SP_UART_LSR_PE | SP_UART_LSR_FE;
+
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		port->read_status_mask |= SP_UART_LSR_BC;
+
+	/*
+	 * Characters to ignore
+	 */
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= SP_UART_LSR_FE | SP_UART_LSR_PE;
+
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= SP_UART_LSR_BC;
+
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= SP_UART_LSR_OE;
+	}
+
+	/*
+	 * Ignore all characters if CREAD is not set.
+	 */
+	if ((termios->c_cflag & CREAD) == 0) {
+		port->ignore_status_mask |= SP_UART_CREAD_DISABLED;
+		/* flush rx data FIFO */
+		sp_uart_set_rx_residue(port->membase, 0);
+	}
+
+	if (termios->c_cflag & CRTSCTS) {
+		sp_uart_set_modem_ctrl(port->membase,
+			sp_uart_get_modem_ctrl(port->membase)
+			| (SP_UART_MCR_AC | SP_UART_MCR_AR));
+	} else {
+		sp_uart_set_modem_ctrl(port->membase,
+			sp_uart_get_modem_ctrl(port->membase)
+			& (~(SP_UART_MCR_AC | SP_UART_MCR_AR)));
+	}
+
+	/* do not set these in emulation */
+	sp_uart_set_divider_high_register(port->membase, div_h);
+	sp_uart_set_divider_low_register(port->membase, div_l);
+	sp_uart_set_line_ctrl(port->membase, lcr);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void sunplus_uart_ops_set_ldisc(struct uart_port *port,
+				       struct ktermios *termios)
+{
+	int new = termios->c_line;
+
+	if (new == N_PPS) {
+		port->flags |= UPF_HARDPPS_CD;
+		sunplus_uart_ops_enable_ms(port);
+	} else {
+		port->flags &= ~UPF_HARDPPS_CD;
+	}
+}
+
+static const char *sunplus_uart_ops_type(struct uart_port *port)
+{
+	struct sunplus_uart_port *sunplus_uart_port =
+		(struct sunplus_uart_port *)port->private_data;
+	return sunplus_uart_port->name;
+}
+
+static void sunplus_uart_ops_release_port(struct uart_port *port)
+{
+}
+
+static int sunplus_uart_ops_request_port(struct uart_port *port)
+{
+	return 0;
+}
+
+static void sunplus_uart_ops_config_port(struct uart_port *port, int type)
+{
+	if (type & UART_CONFIG_TYPE) {
+		port->type = PORT_SUNPLUS;
+		sunplus_uart_ops_request_port(port);
+	}
+}
+
+static int sunplus_uart_ops_verify_port(struct uart_port *port, struct serial_struct *serial)
+{
+	return -EINVAL;
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+static int sunplus_uart_ops_poll_init(struct uart_port *port)
+{
+	return 0;
+}
+
+static void sunplus_uart_ops_poll_put_char(struct uart_port *port,
+	unsigned char data)
+{
+	wait_for_xmitr(port);
+	sp_uart_put_char(port, data);
+}
+
+static int sunplus_uart_ops_poll_get_char(struct uart_port *port)
+{
+	unsigned int status;
+	unsigned char data;
+
+	do {
+		status = sp_uart_get_line_status(port->membase);
+	} while (!(status & SP_UART_LSR_RX));
+
+	data = sp_uart_get_char(port->membase);
+	return (int)data;
+}
+#endif /* CONFIG_CONSOLE_POLL */
+
+static enum hrtimer_restart Check_TXE(struct hrtimer *t)
+{
+	unsigned char lsr;
+	struct sunplus_uart_port *rs485;
+	unsigned char mcr, val;
+	ktime_t ktime;
+	unsigned long nsec;
+
+	rs485 = container_of(t, struct sunplus_uart_port, CheckTXE);
+	mcr = sp_uart_get_modem_ctrl(rs485->uport.membase);
+	lsr = sp_uart_get_line_status(rs485->uport.membase);
+	// TX is NOT empty
+	if (!(lsr & SP_UART_LSR_TXE))
+		return HRTIMER_RESTART;
+	// TX is empty
+	nsec = rs485->uport.rs485.delay_rts_after_send * 1000000;
+	// schedule RTS set
+	if (nsec > 0) {
+		ktime = ktime_set(0, nsec);
+		hrtimer_start(&rs485->DelayRtsAfterSend, ktime, HRTIMER_MODE_REL);
+		return HRTIMER_NORESTART;
+	}
+	// immediately set RTS
+	val = (rs485->uport.rs485.flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0);
+	if (rs485->uport.rs485.flags & SER_RS485_RTS_ON_SEND)
+		mcr |= SP_UART_MCR_RTS;
+	else
+		mcr &= ~SP_UART_MCR_RTS;
+	if (rs485->uport.rs485.flags & SER_RS485_ENABLED && !IS_ERR(rs485->rts_gpio)) {
+		gpiod_set_value(rs485->rts_gpio, val);
+		dev_dbg(rs485->uport.dev, "%s set rts_gpio=%d\n",
+			rs485->uport.name, val);
+	} else {
+		sp_uart_set_modem_ctrl(rs485->uport.membase, mcr);
+	}
+	return HRTIMER_NORESTART;
+}
+
+static enum hrtimer_restart Delay_Rts_Before_Send(struct hrtimer *t)
+{
+	struct sunplus_uart_port *rs485;
+	ktime_t ktime;
+
+	rs485 = container_of(t, struct sunplus_uart_port, DelayRtsBeforeSend);
+	ktime = ktime_set(0, 500000); //500us
+	hrtimer_start(&rs485->CheckTXE, ktime, HRTIMER_MODE_REL);
+	__start_tx(&rs485->uport);
+	return HRTIMER_NORESTART;
+}
+
+static enum hrtimer_restart Delay_Rts_After_Send(struct hrtimer *t)
+{
+	struct sunplus_uart_port *rs485;
+	unsigned char mcr, val;
+
+	rs485 = container_of(t, struct sunplus_uart_port, DelayRtsAfterSend);
+	mcr = sp_uart_get_modem_ctrl(rs485->uport.membase);
+
+	val = (rs485->uport.rs485.flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0);
+	if (rs485->uport.rs485.flags & SER_RS485_RTS_ON_SEND)
+		mcr |= SP_UART_MCR_RTS;
+	else
+		mcr &= ~SP_UART_MCR_RTS;
+	if (rs485->uport.rs485.flags & SER_RS485_ENABLED && !IS_ERR(rs485->rts_gpio)) {
+		gpiod_set_value(rs485->rts_gpio, val);
+		dev_dbg(rs485->uport.dev, "%s set rts_gpio=%d\n",
+			rs485->uport.name, val);
+	} else {
+		sp_uart_set_modem_ctrl(rs485->uport.membase, mcr);
+	}
+	return HRTIMER_NORESTART;
+}
+
+static int sunplus_uart_rs485_onn(struct uart_port *_up,
+	struct sunplus_uart_port *_sup)
+{
+	if (IS_ERR(_sup->rts_gpio)) {
+		DBG_ERR("%s %s No valid rts_gpio, disabling 485\n",
+			_up->name, __func__);
+		_up->rs485.flags &= ~SER_RS485_ENABLED;
+		return (-EINVAL);
+	}
+	DBG_INFO("%s %s rts_gpio is at G_MX[%d].\n",
+		_up->name, __func__, desc_to_gpio(_sup->rts_gpio));
+	if (!_sup->CheckTXE.function) {
+		hrtimer_init(&(_sup->CheckTXE), CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		_sup->CheckTXE.function = Check_TXE;
+	}
+	if (!_sup->DelayRtsBeforeSend.function) {
+		hrtimer_init(&(_sup->DelayRtsBeforeSend), CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		_sup->DelayRtsBeforeSend.function = Delay_Rts_Before_Send;
+	}
+	if (!_sup->DelayRtsAfterSend.function) {
+		hrtimer_init(&(_sup->DelayRtsAfterSend), CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		_sup->DelayRtsAfterSend.function = Delay_Rts_After_Send;
+	}
+	return (0);
+}
+
+static int sunplus_uart_rs485_off(struct uart_port *_up,
+	struct sunplus_uart_port *_sup)
+{
+	_up->rs485.flags &= ~SER_RS485_ENABLED;
+	if (_sup->CheckTXE.function) {
+		hrtimer_cancel(&_sup->CheckTXE);
+		_sup->CheckTXE.function = NULL;
+	}
+	if (_sup->DelayRtsBeforeSend.function) {
+		hrtimer_cancel(&_sup->DelayRtsBeforeSend);
+		_sup->DelayRtsBeforeSend.function = NULL;
+	}
+	if (_sup->DelayRtsAfterSend.function) {
+		hrtimer_cancel(&_sup->DelayRtsAfterSend);
+		_sup->DelayRtsAfterSend.function = NULL;
+	}
+	return (0);
+}
+
+static int sunplus_uart_config_rs485(struct uart_port *_up,
+	struct serial_rs485 *_rs485)
+{
+	struct sunplus_uart_port *_sup =
+		(struct sunplus_uart_port *)_up->private_data;
+	int val;
+
+	if (IS_ERR(_sup->rts_gpio)) {
+		DBG_ERR("%s %s No valid rts_gpio - skipping rs485\n",
+			_up->name, __func__);
+		_up->rs485.flags &= ~SER_RS485_ENABLED;
+		return (-EINVAL);
+	}
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	pm_runtime_get_sync(_sup->dev);
+#endif
+
+	_rs485->delay_rts_before_send =
+		min(_rs485->delay_rts_before_send, 10000U);
+	_rs485->delay_rts_after_send  =
+		min(_rs485->delay_rts_after_send, 10000U);
+
+	if (_rs485->flags & SER_RS485_ENABLED) {
+		dev_dbg(_up->dev, "%s enabling rs485...\n", _up->name);
+		dev_dbg(_up->dev, "%s on_    send:%d (delay:%d)\n",
+			_up->name, _rs485->flags & SER_RS485_RTS_ON_SEND,
+			_rs485->delay_rts_before_send);
+		dev_dbg(_up->dev, "%s after_ send:%d (delay:%d)\n",
+			_up->name, _rs485->flags & SER_RS485_RTS_AFTER_SEND,
+			_rs485->delay_rts_after_send);
+		sunplus_uart_rs485_onn(_up, _sup);
+		val = (_rs485->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0);
+		gpiod_set_value(_sup->rts_gpio, val);
+		dev_dbg(_up->dev, "%s set rts_gpio=%d\n", _up->name, val);
+	} else {
+		dev_dbg(_up->dev, "%s disabling rs485...\n", _up->name);
+		sunplus_uart_rs485_off(_up, _sup);
+	}
+	_up->rs485 = *_rs485;
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	pm_runtime_mark_last_busy(_sup->dev);
+	pm_runtime_put_autosuspend(_sup->dev);
+#endif
+	return (0);
+}
+
+static const struct uart_ops sunplus_uart_ops = {
+	.tx_empty		= sunplus_uart_ops_tx_empty,
+	.set_mctrl		= sunplus_uart_ops_set_mctrl,
+	.get_mctrl		= sunplus_uart_ops_get_mctrl,
+	.stop_tx		= sunplus_uart_ops_stop_tx,
+	.start_tx		= sunplus_uart_ops_start_tx,
+	.stop_rx		= sunplus_uart_ops_stop_rx,
+	.enable_ms		= sunplus_uart_ops_enable_ms,
+	.break_ctl		= sunplus_uart_ops_break_ctl,
+	.startup		= sunplus_uart_ops_startup,
+	.shutdown		= sunplus_uart_ops_shutdown,
+	.set_termios		= sunplus_uart_ops_set_termios,
+	.set_ldisc		= sunplus_uart_ops_set_ldisc,
+	.type			= sunplus_uart_ops_type,
+	.release_port		= sunplus_uart_ops_release_port,
+	.request_port		= sunplus_uart_ops_request_port,
+	.config_port		= sunplus_uart_ops_config_port,
+	.verify_port		= sunplus_uart_ops_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+	.poll_init		= sunplus_uart_ops_poll_init,
+	.poll_put_char		= sunplus_uart_ops_poll_put_char,
+	.poll_get_char		= sunplus_uart_ops_poll_get_char,
+#endif /* CONFIG_CONSOLE_POLL */
+};
+
+static struct uart_driver sunplus_uart_driver;
+
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+static void sunplus_uart_console_putchar(struct uart_port *port, int ch)
+{
+	wait_for_xmitr(port);
+	sp_uart_put_char(port, ch);
+}
+
+static void sunplus_console_write(struct console *co,
+	const char *s, unsigned int count)
+{
+	unsigned long flags;
+	int locked = 1;
+	struct sunplus_uart_port *sp_port;
+	struct sunplus_uartdma_info *uartdma_tx;
+	struct regs_uatxdma *txdma_reg;
+	struct regs_uatxgdma *gdma_reg;
+
+	local_irq_save(flags);
+
+#if defined(SUPPORT_SYSRQ)
+	if (sunplus_uart_ports[co->index].uport.sysrq)
+#else
+	if (0)
+#endif
+	{
+		locked = 0;
+	} else if (oops_in_progress) {
+		locked = spin_trylock(&sunplus_uart_ports[co->index].uport.lock);
+	} else {
+		spin_lock(&sunplus_uart_ports[co->index].uport.lock);
+	}
+
+	sp_port = (struct sunplus_uart_port *)(sunplus_uart_ports[co->index].uport.private_data);
+	uartdma_tx = sp_port->uartdma_tx;
+	if (uartdma_tx) {
+		txdma_reg = (struct regs_uatxdma *)(uartdma_tx->membase);
+		gdma_reg = (struct regs_uatxgdma *)(uartdma_tx->gdma_membase);
+		if (readl(&(txdma_reg->txdma_enable)) == 0x00000005) {
+			/* ring buffer for UART's Tx has been enabled */
+			uart_console_write(&sunplus_uart_ports[co->index].uport,
+				s, count, sunplus_uart_console_putchar);
+		} else {
+			/* Refer to .startup() */
+			if (uartdma_tx->buf_va == NULL) {
+				uartdma_tx->buf_va =
+					dma_alloc_coherent(sunplus_uart_ports[co->index].uport.dev,
+					UATXDMA_BUF_SZ, &(uartdma_tx->dma_handle), GFP_KERNEL);
+				/*
+				 * This message can't be sent to console
+				 * because it's not ready yet
+				 */
+				if (uartdma_tx->buf_va == NULL)
+					panic("Die here.");
+
+				/*
+				 * set 1ms , set wr_adr , set start_addr/end_addr ,
+				 * set bind to uart# , set int enable ,
+				 * set txdma enable (Use ring buffer for UART's Tx)
+				 */
+				writel((CLK_HIGH_UART / 1000),
+					&(txdma_reg->txdma_tmr_unit));
+				writel((u32)(uartdma_tx->dma_handle),
+					&(txdma_reg->txdma_wr_adr));
+				writel((u32)(uartdma_tx->dma_handle),
+					&(txdma_reg->txdma_start_addr));
+				writel(((u32)(uartdma_tx->dma_handle) + UATXDMA_BUF_SZ - 1),
+					&(txdma_reg->txdma_end_addr));
+				writel(uartdma_tx->which_uart,
+					&(txdma_reg->txdma_sel));
+				writel(0x41, &(gdma_reg->gdma_int_en));
+				writel(0x00000005, &(txdma_reg->txdma_enable));
+			}
+		}
+	} else {
+		uart_console_write(&sunplus_uart_ports[co->index].uport,
+			s, count, sunplus_uart_console_putchar);
+	}
+
+	if (locked)
+		spin_unlock(&sunplus_uart_ports[co->index].uport.lock);
+
+	local_irq_restore(flags);
+}
+
+static int __init sunplus_console_setup(struct console *co, char *options)
+{
+	int ret = 0;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	if ((co->index >= NUM_UART) || (co->index < 0))
+		return -EINVAL;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	ret = uart_set_options(&sunplus_uart_ports[co->index].uport,
+		co, baud, parity, bits, flow);
+
+	return ret;
+}
+
+static struct console sunplus_console = {
+	.name		= DEVICE_NAME,
+	.write		= sunplus_console_write,
+	.device		= uart_console_device,	/* default */
+	.setup		= sunplus_console_setup,
+	/*
+	 * CON_ENABLED,
+	 * CON_CONSDEV: preferred console,
+	 * CON_BOOT: primary boot console,
+	 * CON_PRINTBUFFER: used for printk buffer
+	 */
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &sunplus_uart_driver
+};
+#endif
+
+static struct uart_driver sunplus_uart_driver = {
+	.owner		= THIS_MODULE,
+	.driver_name	= "Sunplus_UART",
+	.dev_name	= DEVICE_NAME,
+	.major		= SP_UART_MAJOR,
+	.minor		= SP_UART_MINOR_START,
+	.nr		= NUM_UART,
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+	.cons		= &sunplus_console
+#endif
+};
+
+struct platform_device *sunpluse_uart_platform_device;
+
+static int sunplus_uart_platform_driver_probe_of(struct platform_device *pdev)
+{
+	struct resource *res_mem;
+	struct uart_port *port;
+	struct clk *clk;
+	int ret, irq;
+	int idx_offset, idx;
+	int idx_which_uart;
+	char peri_name[16];
+#ifdef TTYS_GPIO
+	int uart_gpio;
+#endif
+
+	if (pdev->dev.of_node) {
+		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
+		if (pdev->id < 0)
+			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
+	}
+
+	DBG_INFO("sunplus_uart-ID = %d\n", pdev->id);
+
+	idx_offset = -1;
+	if (IS_UARTDMARX_ID(pdev->id)) {
+		idx_offset = 0;
+		DBG_INFO("Setup DMA Rx %d\n", (pdev->id - ID_BASE_DMARX));
+	} else if (IS_UARTDMATX_ID(pdev->id)) {
+		idx_offset = NUM_UARTDMARX;
+		DBG_INFO("Setup DMA Tx %d\n", (pdev->id - ID_BASE_DMATX));
+	}
+	if (idx_offset >= 0) {
+		DBG_INFO("Enable DMA clock(s)\n");
+		clk = devm_clk_get(&pdev->dev, NULL);
+		if (IS_ERR(clk)) {
+			DBG_ERR("Can't find clock source\n");
+			return PTR_ERR(clk);
+		}
+
+		ret = clk_prepare_enable(clk);
+		if (ret) {
+			DBG_ERR("Clock can't be enabled correctly\n");
+			return ret;
+		}
+
+		if (idx_offset == 0)
+			idx = idx_offset + pdev->id - ID_BASE_DMARX;
+		else
+			idx = idx_offset + pdev->id - ID_BASE_DMATX;
+
+		res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res_mem)
+			return -ENODEV;
+
+		sprintf(peri_name, "PERI%d", (idx & 0x01));
+		DBG_INFO("Enable clock %s\n", peri_name);
+		clk = devm_clk_get(&pdev->dev, peri_name);
+		if (IS_ERR(clk)) {
+			DBG_ERR("Can't find clock source: %s\n", peri_name);
+			return PTR_ERR(clk);
+		}
+
+		ret = clk_prepare_enable(clk);
+		if (ret) {
+			DBG_ERR("%s can't be enabled correctly\n", peri_name);
+			return ret;
+		}
+
+		sunplus_uartdma[idx].addr_phy =
+			(unsigned long)(res_mem->start);
+		sunplus_uartdma[idx].membase =
+			devm_ioremap_resource(&pdev->dev, res_mem);
+
+		if (IS_ERR(sunplus_uartdma[idx].membase))
+			return PTR_ERR(sunplus_uartdma[idx].membase);
+
+		if (IS_UARTDMARX_ID(pdev->id)) {
+			irq = platform_get_irq(pdev, 0);
+			if (irq < 0)
+				return -ENODEV;
+
+			sunplus_uartdma[idx].irq = irq;
+		} else {
+			res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+			if (!res_mem)
+				return -ENODEV;
+
+			sunplus_uartdma[idx].gdma_membase =
+				devm_ioremap_resource(&pdev->dev, res_mem);
+
+			if (IS_ERR(sunplus_uartdma[idx].gdma_membase))
+				return -EINVAL;
+
+			DBG_INFO("gdma_phy: 0x%x gdma_membase: 0x%p\n",
+				res_mem->start,
+				sunplus_uartdma[idx].gdma_membase);
+		}
+
+		if (of_property_read_u32(pdev->dev.of_node, "which-uart", &idx_which_uart) != 0) {
+			DBG_ERR("\"which-uart\" is not assigned.");
+			return -EINVAL;
+		}
+		if (idx_which_uart >= NUM_UART) {
+			DBG_ERR("\"which-uart\" is not valid.");
+			return -EINVAL;
+		}
+		sunplus_uartdma[idx].which_uart = idx_which_uart;
+
+		DBG_INFO("adr: 0x%lx, base: 0x%p, irq: %d, uart: %d\n",
+			sunplus_uartdma[idx].addr_phy,
+			sunplus_uartdma[idx].membase,
+			sunplus_uartdma[idx].irq,
+			sunplus_uartdma[idx].which_uart);
+
+		return 0;
+	} else if (pdev->id < 0 || pdev->id >= NUM_UART) {
+		return -EINVAL;
+	}
+
+	port = &sunplus_uart_ports[pdev->id].uport;
+	if (port->membase)
+		return -EBUSY;
+
+	memset(port, 0, sizeof(*port));
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_mem)
+		return -ENODEV;
+
+	port->dev = &pdev->dev;
+	port->mapbase = res_mem->start;
+	port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
+	if (IS_ERR(port->membase))
+		return PTR_ERR(port->membase);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -ENODEV;
+
+	uart_get_rs485_mode(port);
+	sunplus_uart_ports[pdev->id].rts_gpio =
+		devm_gpiod_get(&pdev->dev, "rts", GPIOD_OUT_LOW);
+	port->rs485_config = sunplus_uart_config_rs485;
+	sunplus_uart_ports[pdev->id].CheckTXE.function = NULL;
+	sunplus_uart_ports[pdev->id].DelayRtsBeforeSend.function = NULL;
+	sunplus_uart_ports[pdev->id].DelayRtsAfterSend.function = NULL;
+	if (port->rs485.flags & SER_RS485_ENABLED)
+		sunplus_uart_rs485_onn(port, &(sunplus_uart_ports[pdev->id]));
+
+	DBG_INFO("Enable UART clock(s)\n");
+	sunplus_uart_ports[pdev->id].clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(sunplus_uart_ports[pdev->id].clk)) {
+		DBG_ERR("Can't find clock source\n");
+		return PTR_ERR(sunplus_uart_ports[pdev->id].clk);
+	}
+
+	ret = clk_prepare_enable(sunplus_uart_ports[pdev->id].clk);
+	if (ret) {
+		DBG_ERR("Clock can't be enabled correctly\n");
+		return ret;
+	}
+
+	sunplus_uart_ports[pdev->id].rstc =
+		devm_reset_control_get(&pdev->dev, NULL);
+
+	if (IS_ERR(sunplus_uart_ports[pdev->id].rstc)) {
+		DBG_ERR("failed to retrieve reset controller: %d\n", ret);
+		return PTR_ERR(sunplus_uart_ports[pdev->id].rstc);
+	}
+
+	ret = reset_control_deassert(sunplus_uart_ports[pdev->id].rstc);
+
+	if (ret) {
+		DBG_ERR("failed to deassert reset line: %d\n", ret);
+		return ret;
+	}
+
+	clk = sunplus_uart_ports[pdev->id].clk;
+	if (IS_ERR(clk))
+		port->uartclk = XTAL;
+	else
+		port->uartclk = clk_get_rate(clk);
+
+	port->iotype = UPIO_MEM;
+	port->irq = irq;
+	port->ops = &sunplus_uart_ops;
+	port->flags = UPF_BOOT_AUTOCONF;
+	port->fifosize = 128;
+	port->line = pdev->id;
+
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+	if (pdev->id == 0)
+		port->cons = &sunplus_console;
+#endif
+#ifdef TTYS_GPIO
+	if (pdev->id == 1) {
+		uart_gpio = of_get_named_gpio(pdev->dev.of_node,
+			"uart-gpio", 0);
+		if (!gpio_is_valid(uart_gpio))
+			pr_info("gpio get error\n");
+		else
+			pr_info("gpio no. %d\n", uart_gpio);
+	}
+#endif
+	port->private_data = container_of(&sunplus_uart_ports[pdev->id].uport,
+		struct sunplus_uart_port, uport);
+	sprintf(sunplus_uart_ports[pdev->id].name, "sp_uart%d", pdev->id);
+
+	sunplus_uart_ports[pdev->id].uartdma_rx =
+		sunplus_uartdma_rx_binding(pdev->id);
+
+	if (sunplus_uart_ports[pdev->id].uartdma_rx)
+		DBG_ERR("%s's Rx is in DMA mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+	else
+		DBG_ERR("%s's Rx is in PIO mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+
+	sunplus_uart_ports[pdev->id].uartdma_tx =
+		sunplus_uartdma_tx_binding(pdev->id);
+
+	if (sunplus_uart_ports[pdev->id].uartdma_tx)
+		DBG_ERR("%s's Tx is in DMA mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+	else
+		DBG_ERR("%s's Tx is in PIO mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+
+	ret = uart_add_one_port(&sunplus_uart_driver, port);
+	if (ret) {
+		port->membase = NULL;
+		return ret;
+	}
+	platform_set_drvdata(pdev, port);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (pdev->id != 0) {
+		pm_runtime_set_autosuspend_delay(&pdev->dev, 5000);
+		pm_runtime_use_autosuspend(&pdev->dev);
+		pm_runtime_set_active(&pdev->dev);
+		pm_runtime_enable(&pdev->dev);
+	}
+#endif
+	return 0;
+}
+
+static int sunplus_uart_platform_driver_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (pdev->id != 0) {
+		pm_runtime_disable(&pdev->dev);
+		pm_runtime_set_suspended(&pdev->dev);
+	}
+#endif
+	uart_remove_one_port(&sunplus_uart_driver,
+		&sunplus_uart_ports[pdev->id].uport);
+
+	if (pdev->id < NUM_UART) {
+		clk_disable_unprepare(sunplus_uart_ports[pdev->id].clk);
+		reset_control_assert(sunplus_uart_ports[pdev->id].rstc);
+	}
+
+	return 0;
+}
+
+static int sunplus_uart_platform_driver_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	/* Don't suspend uart0 for cmd line usage */
+	if ((pdev->id < NUM_UART) && (pdev->id > 0))
+		reset_control_assert(sunplus_uart_ports[pdev->id].rstc);
+
+	return 0;
+}
+
+static int sunplus_uart_platform_driver_resume(struct platform_device *pdev)
+{
+	if (pdev->id < NUM_UART) {
+		clk_prepare_enable(sunplus_uart_ports[pdev->id].clk);
+		reset_control_deassert(sunplus_uart_ports[pdev->id].rstc);
+	}
+	return 0;
+}
+
+static const struct of_device_id sp_uart_of_match[] = {
+	{ .compatible = "sunplus,sp7021-uart" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sp_uart_of_match);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+static int sunplus_uart_runtime_suspend(struct device *dev)
+{
+	struct platform_device *uartpdev = to_platform_device(dev);
+
+	/* Don't suspend uart0 for cmd line usage */
+	if ((uartpdev->id < NUM_UART) && (uartpdev->id > 0))
+		reset_control_assert(sunplus_uart_ports[uartpdev->id].rstc);
+
+	return 0;
+}
+
+static int sunplus_uart_runtime_resume(struct device *dev)
+{
+	struct platform_device *uartpdev = to_platform_device(dev);
+
+	if (uartpdev->id < NUM_UART) {
+		clk_prepare_enable(sunplus_uart_ports[uartpdev->id].clk);
+		reset_control_deassert(sunplus_uart_ports[uartpdev->id].rstc);
+	}
+
+	return 0;
+}
+static const struct dev_pm_ops sp7021_uart_pm_ops = {
+	.runtime_suspend = sunplus_uart_runtime_suspend,
+	.runtime_resume  = sunplus_uart_runtime_resume,
+};
+#define sunplus_uart_pm_ops  (&sp7021_uart_pm_ops)
+#endif
+
+static struct platform_driver sunplus_uart_platform_driver = {
+	.probe		= sunplus_uart_platform_driver_probe_of,
+	.remove		= sunplus_uart_platform_driver_remove,
+	.suspend	= sunplus_uart_platform_driver_suspend,
+	.resume		= sunplus_uart_platform_driver_resume,
+	.driver = {
+		.name	= DEVICE_NAME,
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(sp_uart_of_match),
+#ifdef CONFIG_PM_RUNTIME_UART
+		.pm     = sunplus_uart_pm_ops,
+#endif
+	}
+};
+
+static int __init sunplus_uart_init(void)
+{
+	int ret;
+
+	memset(sunplus_uart_ports, 0, sizeof(sunplus_uart_ports));
+	memset(sunplus_uartdma, 0, sizeof(sunplus_uartdma));
+
+	if (!uart0_as_console || !(uart_enable_status & 0x01))
+		sunplus_uart_driver.cons = NULL;
+
+	/* /proc/tty/driver/(sunplus_uart_driver->driver_name) */
+	ret = uart_register_driver(&sunplus_uart_driver);
+	if (ret < 0)
+		return ret;
+
+	ret = platform_driver_register(&sunplus_uart_platform_driver);
+	if (ret != 0) {
+		uart_unregister_driver(&sunplus_uart_driver);
+		return ret;
+	}
+
+	return 0;
+}
+module_init(sunplus_uart_init);
+
+module_param(uart0_as_console, uint, 0444);
+
+#ifdef CONFIG_SERIAL_EARLYCON
+static void sunplus_uart_putc(struct uart_port *port, int c)
+{
+	unsigned int status;
+
+	for (;;) {
+		status = readl(port->membase + SP_UART_LSR);
+		if ((status & SP_UART_LSR_TXE) == SP_UART_LSR_TXE)
+			break;
+		cpu_relax();
+	}
+	writel(c, port->membase + SP_UART_DATA);
+}
+
+static void sunplus_uart_early_write(struct console *con,
+			      const char *s, unsigned int n)
+{
+	struct earlycon_device *dev = con->data;
+
+	uart_console_write(&dev->port, s, n, sunplus_uart_putc);
+}
+
+int __init sunplus_uart_early_setup(struct earlycon_device *device,
+					 const char *opt)
+{
+	if (!(device->port.membase || device->port.iobase))
+		return -ENODEV;
+
+	device->con->write = sunplus_uart_early_write;
+	return 0;
+}
+OF_EARLYCON_DECLARE(sunplus_uart, "sunplus,sp7021-uart", sunplus_uart_early_setup);
+#endif
+
+MODULE_DESCRIPTION("Sunplus UART driver");
+MODULE_AUTHOR("Hammer Hsieh <hammer.hsieh@sunplus.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/soc/sunplus/sp_uart.h b/include/soc/sunplus/sp_uart.h
new file mode 100644
index 0000000..d8a455c
--- /dev/null
+++ b/include/soc/sunplus/sp_uart.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Sunplus SoC UART driver header file
+ */
+
+#ifndef __SP_UART_H__
+#define __SP_UART_H__
+
+#ifdef CONFIG_DEBUG_SP_UART
+#include <mach/io_map.h>
+
+#define LL_UART_PADDR		PA_IOB_ADDR(18 * 32 * 4)
+#define LL_UART_VADDR		VA_IOB_ADDR(18 * 32 * 4)
+#define LOGI_ADDR_UART0_REG	VA_IOB_ADDR(18 * 32 * 4)
+#endif
+
+/* uart register map */
+#define SP_UART_DATA	0x00
+#define SP_UART_LSR		0x04
+#define SP_UART_MSR		0x08
+#define SP_UART_LCR		0x0C
+#define SP_UART_MCR		0x10
+#define SP_UART_DIV_L	0x14
+#define SP_UART_DIV_H	0x18
+#define SP_UART_ISC		0x1C
+
+/* lsr
+ * 1: trasmit fifo is empty
+ */
+#define SP_UART_LSR_TXE		(1 << 6)
+
+/* interrupt
+ * SP_UART_LSR_BC : break condition
+ * SP_UART_LSR_FE : frame error
+ * SP_UART_LSR_OE : overrun error
+ * SP_UART_LSR_PE : parity error
+ * SP_UART_LSR_RX : 1: receive fifo not empty
+ * SP_UART_LSR_TX : 1: transmit fifo is not full
+ */
+#define SP_UART_LSR_BC		(1 << 5)
+#define SP_UART_LSR_FE		(1 << 4)
+#define SP_UART_LSR_OE		(1 << 3)
+#define SP_UART_LSR_PE		(1 << 2)
+#define SP_UART_LSR_RX		(1 << 1)
+#define SP_UART_LSR_TX		(1 << 0)
+
+#define SP_UART_LSR_BRK_ERROR_BITS	\
+	(SP_UART_LSR_PE | SP_UART_LSR_OE | SP_UART_LSR_FE | SP_UART_LSR_BC)
+
+/* lcr */
+#define SP_UART_LCR_WL5		(0 << 0)
+#define SP_UART_LCR_WL6		(1 << 0)
+#define SP_UART_LCR_WL7		(2 << 0)
+#define SP_UART_LCR_WL8		(3 << 0)
+#define SP_UART_LCR_ST		(1 << 2)
+#define SP_UART_LCR_PE		(1 << 3)
+#define SP_UART_LCR_PR		(1 << 4)
+#define SP_UART_LCR_BC		(1 << 5)
+
+/* isc
+ * SP_UART_ISC_MSM : Modem status ctrl
+ * SP_UART_ISC_LSM : Line status interrupt
+ * SP_UART_ISC_RXM : RX interrupt, when got some input data
+ * SP_UART_ISC_TXM : TX interrupt, when trans start
+ */
+#define SP_UART_ISC_MSM		(1 << 7)
+#define SP_UART_ISC_LSM		(1 << 6)
+#define SP_UART_ISC_RXM		(1 << 5)
+#define SP_UART_ISC_TXM		(1 << 4)
+#define HAS_UART_ISC_FLAGMASK	0x0F
+#define SP_UART_ISC_MS		(1 << 3)
+#define SP_UART_ISC_LS		(1 << 2)
+#define SP_UART_ISC_RX		(1 << 1)
+#define SP_UART_ISC_TX		(1 << 0)
+
+/* modem control register */
+#define SP_UART_MCR_AT		(1 << 7)
+#define SP_UART_MCR_AC		(1 << 6)
+#define SP_UART_MCR_AR		(1 << 5)
+#define SP_UART_MCR_LB		(1 << 4)
+#define SP_UART_MCR_RI		(1 << 3)
+#define SP_UART_MCR_DCD		(1 << 2)
+#define SP_UART_MCR_RTS		(1 << 1)
+#define SP_UART_MCR_DTS		(1 << 0)
+
+/* DMA-RX, dma_enable_sel */
+#define DMA_INT				(1 << 31)
+#define DMA_MSI_ID_SHIFT	12
+#define DMA_MSI_ID_MASK		(0x7F << DMA_MSI_ID_SHIFT)
+#define DMA_SEL_UARTX_SHIFT	8
+#define DMA_SEL_UARTX_MASK	(0x07 << DMA_SEL_UARTX_SHIFT)
+#define DMA_SW_RST_B		(1 << 7)
+#define DMA_INIT			(1 << 6)
+#define DMA_GO				(1 << 5)
+#define DMA_AUTO_ENABLE		(1 << 4)
+#define DMA_TIMEOUT_INT_EN	(1 << 3)
+#define DMA_P_SAFE_DISABLE	(1 << 2)
+#define DMA_PBUS_DATA_SWAP	(1 << 1)
+#define DMA_ENABLE			(1 << 0)
+
+#if !defined(__ASSEMBLY__)
+#define UART_SZ			0x80
+struct regs_uart {
+	u32 uart_data;
+	u32 uart_lsr;
+	u32 uart_msr;
+	u32 uart_lcr;
+	u32 uart_mcr;
+	u32 uart_div_l;
+	u32 uart_div_h;
+	u32 uart_isc;
+	u32 uart_tx_residue;
+	u32 uart_rx_residue;
+	u32 uart_rx_threshold;
+	u32 uart_clk_src;
+};
+
+struct regs_uarxdma {
+	u32 rxdma_enable_sel;
+	u32 rxdma_start_addr;
+	u32 rxdma_timeout_set;
+	u32 rxdma_reserved;
+	u32 rxdma_wr_adr;
+	u32 rxdma_rd_adr;
+	u32 rxdma_length_thr;
+	u32 rxdma_end_addr;
+	u32 rxdma_databytes;
+	u32 rxdma_debug_info;
+};
+
+struct regs_uatxdma {
+	u32 txdma_enable;
+	u32 txdma_sel;
+	u32 txdma_start_addr;
+	u32 txdma_end_addr;
+	u32 txdma_wr_adr;
+	u32 txdma_rd_adr;
+	u32 txdma_status;
+	u32 txdma_tmr_unit;
+	u32 txdma_tmr_cnt;
+	u32 txdma_rst_done;
+};
+
+struct regs_uatxgdma {
+	u32 gdma_hw_ver;
+	u32 gdma_config;
+	u32 gdma_length;
+	u32 gdma_addr;
+	u32 gdma_port_mux;
+	u32 gdma_int_flag;
+	u32 gdma_int_en;
+	u32 gdma_software_reset_status;
+	u32 txdma_tmr_cnt;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __SP_UART_H__ */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-01  7:48 ` [PATCH 2/2] serial:sunplus-uart:Add " hammer.hsieh
@ 2021-11-01  7:56   ` Greg KH
  0 siblings, 0 replies; 19+ messages in thread
From: Greg KH @ 2021-11-01  7:56 UTC (permalink / raw)
  To: hammer.hsieh
  Cc: linux-serial, devicetree, linux-kernel, jirislaby, p.zabel,
	tony.huang, wells.lu, hammer.hsieh

On Mon, Nov 01, 2021 at 03:48:23PM +0800, hammer.hsieh wrote:
> Add Sunplus SoC UART Driver
> 
> Signed-off-by: hammer.hsieh <hammer.hsieh@sunplus.com>

I doubt you sign your name with a "." in it, right?

Also this address does not match your From: address.  Please fix this up
when resending this.

> ---
>  MAINTAINERS                       |    2 +
>  drivers/tty/serial/Kconfig        |   23 +
>  drivers/tty/serial/Makefile       |    1 +
>  drivers/tty/serial/sunplus-uart.c | 1848 +++++++++++++++++++++++++++++++++++++
>  include/soc/sunplus/sp_uart.h     |  158 ++++
>  5 files changed, 2032 insertions(+)
>  create mode 100644 drivers/tty/serial/sunplus-uart.c
>  create mode 100644 include/soc/sunplus/sp_uart.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f863e97..0176026 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17949,6 +17949,8 @@ SUNPLUS UART DRIVER
>  M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/serial/sunplus,uart.yaml
> +F:	drivers/tty/serial/sunplus-uart.c
> +F:	include/soc/sunplus/sp-uart.h
>  
>  SUPERH
>  M:	Yoshinori Sato <ysato@users.sourceforge.jp>
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 131a6a5..319f5db 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1561,6 +1561,29 @@ config SERIAL_LITEUART_CONSOLE
>  	  and warnings and which allows logins in single user mode).
>  	  Otherwise, say 'N'.
>  
> +config SERIAL_SUNPLUS
> +	bool "Sunplus UART support"
> +	depends on OF
> +	select SERIAL_CORE
> +	help
> +	  Select this option if you would like to use Sunplus serial port on
> +	  Sunplus SoC SP7021.
> +	  If you enable this option, Sunplus serial ports in the system will
> +	  be registered as ttySx.
> +
> +config SERIAL_SUNPLUS_CONSOLE
> +	bool "Console on Sunplus UART"
> +	depends on SERIAL_SUNPLUS
> +	select SERIAL_CORE_CONSOLE
> +	select SERIAL_EARLYCON
> +	help
> +	  Select this option if you would like to use a Sunplus UART as the
> +	  system console.
> +	  Even if you say Y here, the currently visible virtual console
> +	  (/dev/tty0) will still be used as the system console by default, but
> +	  you can alter that using a kernel command line option such as
> +	  "console=ttySx".
> +
>  endmenu
>  
>  config SERIAL_MCTRL_GPIO
> diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
> index 7da0856..61cc8de 100644
> --- a/drivers/tty/serial/Makefile
> +++ b/drivers/tty/serial/Makefile
> @@ -87,6 +87,7 @@ obj-$(CONFIG_SERIAL_RDA)	+= rda-uart.o
>  obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
>  obj-$(CONFIG_SERIAL_SIFIVE)	+= sifive.o
>  obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o
> +obj-$(CONFIG_SERIAL_SUNPLUS)	+= sunplus-uart.o
>  
>  # GPIOLIB helpers for modem control lines
>  obj-$(CONFIG_SERIAL_MCTRL_GPIO)	+= serial_mctrl_gpio.o
> diff --git a/drivers/tty/serial/sunplus-uart.c b/drivers/tty/serial/sunplus-uart.c
> new file mode 100644
> index 0000000..d1524dc
> --- /dev/null
> +++ b/drivers/tty/serial/sunplus-uart.c
> @@ -0,0 +1,1848 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later

I have to ask,. but are you sure about this license that it needs to be
"-or-later"?

> +/*
> + * Sunplus SoC UART driver
> + *
> + * Author: Hammer Hsieh <hammer.hsieh@sunplus.com>
> + * Tony Huang <tony.huang@sunplus.com>
> + * Wells Lu <wells.lu@sunplus.com>
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/console.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/tty.h>
> +#include <linux/tty_flip.h>
> +#include <linux/of_platform.h>
> +#include <asm/irq.h>
> +#if defined(CONFIG_MAGIC_SYSRQ)
> +#define SUPPORT_SYSRQ
> +#include <linux/sysrq.h>
> +#endif
> +#include <linux/serial_core.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/io.h>
> +#include <linux/dma-mapping.h>
> +#include <soc/sunplus/sp_uart.h>
> +
> +#ifdef CONFIG_PM_RUNTIME_UART
> +#include <linux/pm_runtime.h>
> +#endif

Why the #ifdef in the .c file?

> +
> +#include <linux/gpio.h>

GPIO in a serial driver?

> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#include <dt-bindings/clock/sp-sp7021.h>
> +#include <dt-bindings/pinctrl/sppctl-sp7021.h>
> +#include <linux/delay.h>
> +#include <linux/hrtimer.h>

Please put the linux/ includes above the dt-bindings ones.

> +
> +#define DEVICE_NAME				"ttyS"
> +#define SP_UART_MAJOR			TTY_MAJOR

Why is this driver allowed to be named the same as the other serial
drivers?  What happens when you plug in a 8250 card to this device?

> +#define SP_UART_MINOR_START		64

Why here?

> +
> +#define NUM_UART		6	/* serial0,  ... */
> +#define NUM_UARTDMARX	2	/* serial10, ... */
> +#define NUM_UARTDMATX	2	/* serial20, ... */

Why are these hard codeded?

> +
> +#define ID_BASE_DMARX	10
> +#define ID_BASE_DMATX	20
> +
> +#define IS_UARTDMARX_ID(X) \
> +	(((X) >= (ID_BASE_DMARX)) && ((X) < (ID_BASE_DMARX + NUM_UARTDMARX)))
> +#define IS_UARTDMATX_ID(X) \
> +	(((X) >= (ID_BASE_DMATX)) && ((X) < (ID_BASE_DMATX + NUM_UARTDMATX)))
> +
> +//#define TTYS_KDBG_INFO
> +#define TTYS_KDBG_ERR
> +//#define TTYS_GPIO

Why is this commented out?

Why is this defined at all?

> +
> +#ifdef TTYS_KDBG_INFO
> +#define DBG_INFO(fmt, args ...)	pr_info("K_TTYS: " fmt, ## args)
> +#else
> +#define DBG_INFO(fmt, args ...)
> +#endif
> +#ifdef TTYS_KDBG_ERR
> +#define DBG_ERR(fmt, args ...)	pr_err("K_TTYS: " fmt, ## args)
> +#else
> +#define DBG_ERR(fmt, args ...)
> +#endif

No, please use dev_info(), dev_err() and dev_dbg() only.  Do not create
your own logging macros for a single driver, use the ones the kernel
gives you.

> +
> +#define SP_UART_CREAD_DISABLED		(1 << 16)
> +
> +#define UARXDMA_BUF_SZ			PAGE_SIZE
> +#define MAX_SZ_RXDMA_ISR		(1 << 9)
> +#define UATXDMA_BUF_SZ			PAGE_SIZE
> +
> +#define CLK_HIGH_UART			202500000
> +#define UART_RATIO				232
> +
> +#if defined(CONFIG_SP_MON)

What sets this?

I've stopped reviewing here.

thanks,

greg k-h

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  2021-11-01  7:48 ` [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver hammer.hsieh
@ 2021-11-01 13:20   ` Rob Herring
  2021-11-01 19:34   ` Rob Herring
  1 sibling, 0 replies; 19+ messages in thread
From: Rob Herring @ 2021-11-01 13:20 UTC (permalink / raw)
  To: hammer.hsieh
  Cc: linux-kernel, linux-serial, hammer.hsieh, devicetree, gregkh,
	p.zabel, wells.lu, tony.huang, jirislaby

On Mon, 01 Nov 2021 15:48:22 +0800, hammer.hsieh wrote:
> Add bindings doc for Sunplus SoC UART Driver
> 
> Signed-off-by: hammer.hsieh <hammer.hsieh@sunplus.com>
> ---
>  .../devicetree/bindings/serial/sunplus,uart.yaml   | 116 +++++++++++++++++++++
>  MAINTAINERS                                        |   5 +
>  2 files changed, 121 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/sunplus,uart.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/serial/sunplus,uart.yaml:36:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/serial/sunplus,uart.yaml:39:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/serial/sunplus,uart.yaml:42:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/serial/sunplus,uart.yaml:45:9: [warning] wrong indentation: expected 10 but found 8 (indentation)

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/serial/sunplus,uart.example.dts:20:18: fatal error: dt-bindings/clock/sp-sp7021.h: No such file or directory
   20 |         #include <dt-bindings/clock/sp-sp7021.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/serial/sunplus,uart.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1441: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1548996

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  2021-11-01  7:48 ` [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver hammer.hsieh
  2021-11-01 13:20   ` Rob Herring
@ 2021-11-01 19:34   ` Rob Herring
  1 sibling, 0 replies; 19+ messages in thread
From: Rob Herring @ 2021-11-01 19:34 UTC (permalink / raw)
  To: hammer.hsieh
  Cc: gregkh, linux-serial, devicetree, linux-kernel, jirislaby,
	p.zabel, tony.huang, wells.lu, hammer.hsieh

On Mon, Nov 01, 2021 at 03:48:22PM +0800, hammer.hsieh wrote:
> Add bindings doc for Sunplus SoC UART Driver
> 
> Signed-off-by: hammer.hsieh <hammer.hsieh@sunplus.com>
> ---
>  .../devicetree/bindings/serial/sunplus,uart.yaml   | 116 +++++++++++++++++++++
>  MAINTAINERS                                        |   5 +
>  2 files changed, 121 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/sunplus,uart.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/sunplus,uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,uart.yaml
> new file mode 100644
> index 0000000..f2ca9ee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/sunplus,uart.yaml
> @@ -0,0 +1,116 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) Sunplus Co., Ltd. 2021
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/serial/sunplus,uart.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Sunplus SoC UART Controller Device Tree Bindings
> +
> +maintainers:
> +  - Tony Huang <tony.huang@sunplus.com>
> +  - Hammer Hsieh <hammer.hsieh@sunplus.com>
> +  - Wells Lu <wells.lu@sunplus.com>
> +
> +allOf:
> +  - $ref: serial.yaml#
> +
> +properties:
> +  compatible:
> +    const: sunplus,sp7021-uart
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 2
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    oneOf:
> +      - items:
> +        - const: UADMA
> +        - const: PERI0
> +      - items:
> +        - const: UADMA
> +        - const: PERI1

These 2 can be:

items:
  - const UADMA
  - pattern: '^PERI[0-1]$'

But why the difference for only one model of UART? The names should 
reflect the function of the clock. 

> +      - items:
> +        - const: HWUA
> +        - const: PERI0
> +      - items:
> +        - const: HWUA
> +        - const: PERI1
> +
> +  resets:
> +    maxItems: 1
> +
> +  which-uart:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 1, 2, 3, 4]

What's this for? Looks like an index and we don't do indices in DT. 
There is 'aliases' though.

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/clock/sp-sp7021.h>
> +    #include <dt-bindings/reset/sp-sp7021.h>
> +    aliases {
> +            serial0 = &uart0;
> +            serial1 = &uart1;
> +            serial10 = &uartdmarx0;
> +            serial20 = &uartdmatx0;
> +    };
> +
> +    uart0: serial@9c000900 {
> +      compatible = "sunplus,sp7021-uart";
> +      reg = <0x9c000900 0x80>;
> +      interrupt-parent = <&intc>;
> +      interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> +      clocks = <&clkc UA0>;

The schema says you must have 2 clocks.

> +      resets = <&rstc RST_UA0>;
> +    };
> +
> +    // UART1 PIO mode
> +    uart1: serial@9c000980 {
> +        compatible = "sunplus,sp7021-uart";
> +        reg = <0x9c000980 0x80>;
> +        interrupt-parent = <&intc>;
> +        interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clkc UA1>;
> +        resets = <&rstc RST_UA1>;
> +    };
> +
> +    // UART1 DMA mode for RX
> +    uartdmarx0: serial@9c008980 {
> +        compatible = "sunplus,sp7021-uart";
> +        reg = <0x9c008980 0x40>;
> +        interrupt-parent = <&intc>;
> +        interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clkc UADMA>, <&clkc PERI0>;
> +        clock-names = "UADMA", "PERI0";
> +        resets = <&rstc RST_UADMA>;
> +        which-uart = <1>;
> +    };
> +
> +    // UART1 DMA mode for TX
> +    uartdmatx0: serial@9c008a00 {
> +        compatible = "sunplus,sp7021-uart";
> +        reg = <0x9c008a00 0x40>, <0x9c008880 0x80>;
> +        clocks = <&clkc HWUA>, <&clkc PERI0>;
> +        clock-names = "HWUA", "PERI0";
> +        resets = <&rstc RST_HWUA>;
> +        which-uart = <1>;
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3b79fd4..f863e97 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17945,6 +17945,11 @@ L:	netdev@vger.kernel.org
>  S:	Maintained
>  F:	drivers/net/ethernet/dlink/sundance.c
>  
> +SUNPLUS UART DRIVER
> +M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/serial/sunplus,uart.yaml
> +
>  SUPERH
>  M:	Yoshinori Sato <ysato@users.sourceforge.jp>
>  M:	Rich Felker <dalias@libc.org>
> -- 
> 2.7.4
> 
> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC
  2021-11-01  7:48 [PATCH 0/2] Add UART driver for Suplus SP7021 SoC hammer.hsieh
  2021-11-01  7:48 ` [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver hammer.hsieh
  2021-11-01  7:48 ` [PATCH 2/2] serial:sunplus-uart:Add " hammer.hsieh
@ 2021-11-10  7:51 ` Hammer Hsieh
  2021-11-10  7:51   ` [PATCH v2 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
                     ` (2 more replies)
  2021-11-19  5:19 ` [PATCH v3 " Hammer Hsieh
  3 siblings, 3 replies; 19+ messages in thread
From: Hammer Hsieh @ 2021-11-10  7:51 UTC (permalink / raw)
  To: gregkh, robh+dt, linux-serial, devicetree, linux-kernel,
	jirislaby, p.zabel
  Cc: tony.huang, wells.lu, Hammer Hsieh

This is a patch series for UART driver for Suplus SP7021 SoC.

Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates
many peripherals (ex: UART. I2C, SPI, SDIO, eMMC, USB, SD card and
etc.) into a single chip. It is designed for industrial control.

Refer to:
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
https://tibbo.com/store/plus1.html

Hammer Hsieh (2):
  dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  serial:sunplus-uart:Add Sunplus SoC UART Driver

 .../bindings/serial/sunplus,sp7021-uart.yaml       |  157 ++
 MAINTAINERS                                        |    7 +
 drivers/tty/serial/Kconfig                         |   23 +
 drivers/tty/serial/Makefile                        |    1 +
 drivers/tty/serial/sunplus-uart.c                  | 1591 ++++++++++++++++++++
 include/soc/sunplus/sp_uart.h                      |  147 ++
 6 files changed, 1926 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
 create mode 100644 drivers/tty/serial/sunplus-uart.c
 create mode 100644 include/soc/sunplus/sp_uart.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  2021-11-10  7:51 ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Hammer Hsieh
@ 2021-11-10  7:51   ` Hammer Hsieh
  2021-11-10  7:51   ` [PATCH v2 2/2] serial:sunplus-uart:Add " Hammer Hsieh
  2021-11-10 16:41   ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Andy Shevchenko
  2 siblings, 0 replies; 19+ messages in thread
From: Hammer Hsieh @ 2021-11-10  7:51 UTC (permalink / raw)
  To: gregkh, robh+dt, linux-serial, devicetree, linux-kernel,
	jirislaby, p.zabel
  Cc: tony.huang, wells.lu, Hammer Hsieh

Add bindings doc for Sunplus SoC UART Driver

Signed-off-by: Hammer Hsieh <hammer.hsieh@sunplus.com>
---
Changes in v2:
 - Addressed all comments from Mr. Rob Herring.

 .../bindings/serial/sunplus,sp7021-uart.yaml       | 157 +++++++++++++++++++++
 MAINTAINERS                                        |   5 +
 2 files changed, 162 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml

diff --git a/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
new file mode 100644
index 0000000..3f46f3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/sunplus,sp7021-uart.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Sunplus SoC SP7021 UART Controller Device Tree Bindings
+
+maintainers:
+  - Tony Huang <tony.huang@sunplus.com>
+  - Hammer Hsieh <hammer.hsieh@sunplus.com>
+  - Wells Lu <wells.lu@sunplus.com>
+
+allOf:
+  - $ref: serial.yaml#
+
+properties:
+  compatible:
+    const: sunplus,sp7021-uart
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    oneOf:
+      - items:
+          - const: UADMA
+          - pattern: '^PERI[0-1]$'
+      - items:
+          - const: HWUA
+          - pattern: '^PERI[0-1]$'
+
+  resets:
+    maxItems: 1
+
+  which-uart:
+    description:
+      UA1-4 support DMA mode, UA0 support PIO mode only.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 1, 2, 3, 4]
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - sunplus,sp7021-uart-rxdma
+          - sunplus,sp7021-uart-txdma
+then:
+  required:
+    - clock-names
+    - which-uart
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    aliases {
+            serial0 = &uart0;
+            serial1 = &uart1;
+            serial2 = &uart2;
+            serial10 = &uartdmarx0;
+            serial20 = &uartdmatx0;
+            serial11 = &uartdmarx1;
+            serial21 = &uartdmatx1;
+    };
+
+    // UART0 PIO mode only
+    uart0: serial@9c000900 {
+        compatible = "sunplus,sp7021-uart";
+        reg = <0x9c000900 0x80>;
+        interrupt-parent = <&intc>;
+        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc 0x28>;
+        resets = <&rstc 0x18>;
+    };
+
+    // UART1 PIO mode
+    uart1: serial@9c000980 {
+        compatible = "sunplus,sp7021-uart";
+        reg = <0x9c000980 0x80>;
+        interrupt-parent = <&intc>;
+        interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc 0x29>;
+        resets = <&rstc 0x19>;
+    };
+
+    // UART1 DMA mode for RX
+    uartdmarx0: serial@9c008980 {
+        compatible = "sunplus,sp7021-uart-rxdma";
+        reg = <0x9c008980 0x40>;
+        interrupt-parent = <&intc>;
+        interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc 0x2f>, <&clkc 0x1b>;
+        clock-names = "UADMA", "PERI0";
+        resets = <&rstc 0x1f>;
+        which-uart = <1>;
+    };
+
+    // UART1 DMA mode for TX
+    uartdmatx0: serial@9c008a00 {
+        compatible = "sunplus,sp7021-uart-txdma";
+        reg = <0x9c008a00 0x40>, <0x9c008880 0x80>;
+        clocks = <&clkc 0x2d>, <&clkc 0x1b>;
+        clock-names = "HWUA", "PERI0";
+        resets = <&rstc 0x1d>;
+        which-uart = <1>;
+    };
+
+    // UART2 PIO mode
+    uart2: serial@9c000800 {
+        compatible = "sunplus,sp7021-uart";
+        reg = <0x9c000800 0x80>;
+        interrupt-parent = <&intc>;
+        interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc 0x2a>;
+        resets = <&rstc 0x1a>;
+    };
+
+    // UART2 DMA mode for RX
+    uartdmarx1: serial@9c0089c0 {
+        compatible = "sunplus,sp7021-uart-rxdma";
+        reg = <0x9c0089c0 0x40>;
+        interrupt-parent = <&intc>;
+        interrupts = <139 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc 0x2f>,	<&clkc 0x1f>;
+        clock-names = "UADMA", "PERI1";
+        resets = <&rstc 0x1f>;
+        which-uart = <2>;
+    };
+
+    // UART2 DMA mode for TX
+    uartdmatx1: serial@9c008a40 {
+        compatible = "sunplus,sp7021-uart-txdma";
+        reg = <0x9c008a40 0x40>, <0x9c008900 0x80>;
+        clocks = <&clkc 0x2d>, <&clkc 0x1f>;
+        clock-names = "HWUA", "PERI1";
+        resets = <&rstc 0x1d>;
+        which-uart = <2>;
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 3b79fd4..f2ee40c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17945,6 +17945,11 @@ L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/ethernet/dlink/sundance.c
 
+SUNPLUS UART DRIVER
+M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
+
 SUPERH
 M:	Yoshinori Sato <ysato@users.sourceforge.jp>
 M:	Rich Felker <dalias@libc.org>
-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-10  7:51 ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Hammer Hsieh
  2021-11-10  7:51   ` [PATCH v2 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
@ 2021-11-10  7:51   ` Hammer Hsieh
  2021-11-10  9:50     ` Philipp Zabel
  2021-11-12  8:31     ` kernel test robot
  2021-11-10 16:41   ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Andy Shevchenko
  2 siblings, 2 replies; 19+ messages in thread
From: Hammer Hsieh @ 2021-11-10  7:51 UTC (permalink / raw)
  To: gregkh, robh+dt, linux-serial, devicetree, linux-kernel,
	jirislaby, p.zabel
  Cc: tony.huang, wells.lu, Hammer Hsieh

Add Sunplus SoC UART Driver

Signed-off-by: Hammer Hsieh <hammer.hsieh@sunplus.com>
---
Changes in v2:
 - Addressed all comments from Mr. Greg Kroah-Hartman.

 MAINTAINERS                       |    2 +
 drivers/tty/serial/Kconfig        |   23 +
 drivers/tty/serial/Makefile       |    1 +
 drivers/tty/serial/sunplus-uart.c | 1591 +++++++++++++++++++++++++++++++++++++
 include/soc/sunplus/sp_uart.h     |  147 ++++
 5 files changed, 1764 insertions(+)
 create mode 100644 drivers/tty/serial/sunplus-uart.c
 create mode 100644 include/soc/sunplus/sp_uart.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f2ee40c..14790a4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17949,6 +17949,8 @@ SUNPLUS UART DRIVER
 M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
+F:	drivers/tty/serial/sunplus-uart.c
+F:	include/soc/sunplus/sp-uart.h
 
 SUPERH
 M:	Yoshinori Sato <ysato@users.sourceforge.jp>
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 131a6a5..319f5db 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1561,6 +1561,29 @@ config SERIAL_LITEUART_CONSOLE
 	  and warnings and which allows logins in single user mode).
 	  Otherwise, say 'N'.
 
+config SERIAL_SUNPLUS
+	bool "Sunplus UART support"
+	depends on OF
+	select SERIAL_CORE
+	help
+	  Select this option if you would like to use Sunplus serial port on
+	  Sunplus SoC SP7021.
+	  If you enable this option, Sunplus serial ports in the system will
+	  be registered as ttySx.
+
+config SERIAL_SUNPLUS_CONSOLE
+	bool "Console on Sunplus UART"
+	depends on SERIAL_SUNPLUS
+	select SERIAL_CORE_CONSOLE
+	select SERIAL_EARLYCON
+	help
+	  Select this option if you would like to use a Sunplus UART as the
+	  system console.
+	  Even if you say Y here, the currently visible virtual console
+	  (/dev/tty0) will still be used as the system console by default, but
+	  you can alter that using a kernel command line option such as
+	  "console=ttySx".
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 7da0856..61cc8de 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_SERIAL_RDA)	+= rda-uart.o
 obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
 obj-$(CONFIG_SERIAL_SIFIVE)	+= sifive.o
 obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o
+obj-$(CONFIG_SERIAL_SUNPLUS)	+= sunplus-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)	+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/sunplus-uart.c b/drivers/tty/serial/sunplus-uart.c
new file mode 100644
index 0000000..bfc19e2
--- /dev/null
+++ b/drivers/tty/serial/sunplus-uart.c
@@ -0,0 +1,1591 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sunplus SoC UART driver
+ *
+ * Author: Hammer Hsieh <hammer.hsieh@sunplus.com>
+ * Tony Huang <tony.huang@sunplus.com>
+ * Wells Lu <wells.lu@sunplus.com>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/of_platform.h>
+#include <asm/irq.h>
+#include <linux/sysrq.h>
+#include <linux/serial_core.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/delay.h>
+#include <linux/hrtimer.h>
+#include <soc/sunplus/sp_uart.h>
+#include <dt-bindings/clock/sp-sp7021.h>
+
+/*
+ * UART_NR : Nunmer of UART channel, serial0, ...
+ * UART_DMARX_NR : Nunmer of UART RX DMA, serial10, ...
+ * UART_DMATX_NR : Nunmer of UART TX DMA, serial20, ...
+ *
+ */
+#define UART_NR			5
+#define UART_DMARX_NR	2
+#define UART_DMATX_NR	2
+
+/*
+ * IS_UARTDMARX_ID(X) : if true , do rxdma init in probe
+ * IS_UARTDMATX_ID(X) : if true , do txdma init in probe
+ *
+ */
+#define ID_BASE_DMARX	10
+#define ID_BASE_DMATX	20
+
+#define IS_UARTDMARX_ID(X) \
+	(((X) >= (ID_BASE_DMARX)) && ((X) < (ID_BASE_DMARX + UART_DMARX_NR)))
+#define IS_UARTDMATX_ID(X) \
+	(((X) >= (ID_BASE_DMATX)) && ((X) < (ID_BASE_DMATX + UART_DMATX_NR)))
+
+struct sunplus_uart_port {
+	char name[16];
+	struct uart_port uport;
+	struct sunplus_dma_info *uartdma_rx;
+	struct sunplus_dma_info *uartdma_tx;
+	struct clk *clk;
+	struct reset_control *rstc;
+	unsigned int pllsys_rate;
+	struct gpio_desc *rts_gpio;
+	struct hrtimer rts_check_tx_empty;
+	struct hrtimer rts_delay_before_send;
+	struct hrtimer rts_delay_after_send;
+};
+struct sunplus_uart_port sunplus_uart_ports[UART_NR];
+static struct uart_driver sunplus_uart_driver;
+
+struct sunplus_dma_info {
+	void __iomem *membase;
+	void __iomem *gdma_membase;
+	unsigned long addr_phy;
+	int irq;
+	int which_uart;
+	struct sunplus_uart_port *binding_port;
+	void *buf_va;
+	dma_addr_t dma_handle;
+};
+static struct sunplus_dma_info
+	sunplus_uartdma[UART_DMARX_NR + UART_DMATX_NR];
+
+static inline struct sunplus_uart_port *to_sunplus_uart(struct uart_port *uport)
+{
+	return container_of(uport, struct sunplus_uart_port, uport);
+}
+
+static inline void sp_uart_put_char(struct uart_port *port, unsigned int ch)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	struct sunplus_dma_info *tx_dma = sp_port->uartdma_tx;
+	u32 addr_sw, addr_start;
+	u32 offset_sw;
+	u8 *byte_ptr;
+
+	if (!tx_dma) {
+		writel(ch, port->membase + SP_UART_DATA);
+	} else {
+		addr_sw = readl(tx_dma->membase + SP_UART_TXDMA_WR_ADR);
+		addr_start = readl(tx_dma->membase + SP_UART_TXDMA_START_ADDR);
+		offset_sw = addr_sw - addr_start;
+		byte_ptr = (u8 *)(tx_dma->buf_va + offset_sw);
+		*byte_ptr = (u8)(ch);
+		if (offset_sw == (PAGE_SIZE - 1))
+			writel((u32)(tx_dma->dma_handle),
+				tx_dma->membase + SP_UART_TXDMA_WR_ADR);
+		else
+			writel((addr_sw + 1),
+				tx_dma->membase + SP_UART_TXDMA_WR_ADR);
+	}
+}
+
+static inline u32 sp_uart_line_status_tx_buf_not_full(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	struct sunplus_dma_info *tx_dma = sp_port->uartdma_tx;
+	u32 addr_sw, addr_hw;
+
+	if (tx_dma) {
+		if (readl(tx_dma->membase + SP_UART_TXDMA_STATUS) & TXDMA_BUF_FULL)
+			return 0;
+
+		addr_sw = readl(tx_dma->membase + SP_UART_TXDMA_WR_ADR);
+		addr_hw = readl(tx_dma->membase + SP_UART_TXDMA_RD_ADR);
+		if (addr_sw >= addr_hw)
+			return (PAGE_SIZE - (addr_sw - addr_hw));
+		else
+			return (addr_hw - addr_sw);
+
+	} else {
+		if (readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TX)
+			return 1;
+		else
+			return 0;
+	}
+}
+
+/*
+ * Note:
+ * When (uart0_as_console == 0), please make sure:
+ *     There is no "console=ttyS0,115200", "earlyprintk", ... in kernel command line.
+ *     In /etc/inittab, there is no something like "ttyS0::respawn:/bin/sh"
+ */
+unsigned int uart0_as_console = ~0;
+unsigned int uart_enable_status = ~0;
+
+static struct sunplus_dma_info *sunplus_uartdma_rx_binding(int id)
+{
+	int i;
+
+	for (i = 0; i < UART_DMARX_NR; i++) {
+		if ((sunplus_uartdma[i].which_uart == id) && (sunplus_uartdma[i].membase)) {
+			sunplus_uartdma[i].binding_port = &sunplus_uart_ports[id];
+			return &sunplus_uartdma[i];
+		}
+	}
+	return NULL;
+}
+
+static struct sunplus_dma_info *sunplus_uartdma_tx_binding(int id)
+{
+	int i;
+
+	for (i = UART_DMARX_NR; i < (UART_DMARX_NR + UART_DMATX_NR); i++) {
+		if ((sunplus_uartdma[i].which_uart == id) && (sunplus_uartdma[i].membase)) {
+			sunplus_uartdma[i].binding_port = &sunplus_uart_ports[id];
+			return &sunplus_uartdma[i];
+		}
+	}
+	return NULL;
+}
+
+static inline void wait_for_xmitr(struct uart_port *port)
+{
+	while (1) {
+		if (sp_uart_line_status_tx_buf_not_full(port))
+			break;
+	}
+}
+
+static unsigned int sunplus_tx_empty(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	struct sunplus_dma_info *tx_dma = sp_port->uartdma_tx;
+
+	if (tx_dma) {
+		if (readl(tx_dma->membase + SP_UART_TXDMA_STATUS) & TXDMA_BUF_EMPTY)
+			return TIOCSER_TEMT;
+		else
+			return 0;
+	} else {
+		return ((readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TXE)
+			? TIOCSER_TEMT : 0);
+	}
+}
+
+static void sunplus_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	unsigned int mcr = readl(port->membase + SP_UART_MCR);
+	ktime_t ktime;
+
+	if (mctrl & TIOCM_DTR)
+		mcr |= SP_UART_MCR_DTS;
+	else
+		mcr &= ~SP_UART_MCR_DTS;
+
+	if (mctrl & TIOCM_RTS) {
+		if ((sp_port->uport.rs485.flags & SER_RS485_ENABLED)
+			&& (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND))
+			mcr &= ~SP_UART_MCR_RTS;  /* RTS invert */
+		else
+			mcr |= SP_UART_MCR_RTS;
+	} else {
+		/* data transfer ended */
+		if (sp_port->uport.rs485.flags & SER_RS485_ENABLED)
+			return;
+
+		mcr &= ~SP_UART_MCR_RTS;
+	}
+
+	if (mctrl & TIOCM_CAR)
+		mcr |= SP_UART_MCR_DCD;
+	else
+		mcr &= ~SP_UART_MCR_DCD;
+
+	if (mctrl & TIOCM_RI)
+		mcr |= SP_UART_MCR_RI;
+	else
+		mcr &= ~SP_UART_MCR_RI;
+
+	if (mctrl & TIOCM_LOOP)
+		mcr |= SP_UART_MCR_LB;
+	else
+		mcr &= ~SP_UART_MCR_LB;
+
+	writel(mcr, port->membase + SP_UART_MCR);
+
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED) {
+		mcr = readl(port->membase + SP_UART_MCR);
+		if (mctrl & TIOCM_RTS) {
+			if (((mcr & SP_UART_MCR_RTS)
+				&& (sp_port->uport.rs485.flags & SER_RS485_RTS_AFTER_SEND))
+				|| (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND)) {
+				if (!IS_ERR(sp_port->rts_gpio))
+					gpiod_set_value(sp_port->rts_gpio, 1);
+				dev_dbg(port->dev, "%s set rts_gpio=1\n", port->name);
+				if (sp_port->uport.rs485.delay_rts_before_send == 0) {
+					ktime = ktime_set(0, 500000); /* 500us */
+					hrtimer_start(&sp_port->rts_check_tx_empty,
+						ktime, HRTIMER_MODE_REL);
+				}
+			}
+		}
+	}
+}
+
+static unsigned int sunplus_get_mctrl(struct uart_port *port)
+{
+	unsigned int ret, mcr;
+
+	mcr = readl(port->membase + SP_UART_MCR);
+
+	if (mcr & SP_UART_MCR_DTS)
+		ret |= TIOCM_DTR;
+
+	if (mcr & SP_UART_MCR_RTS)
+		ret |= TIOCM_RTS;
+
+	if (mcr & SP_UART_MCR_DCD)
+		ret |= TIOCM_CAR;
+
+	if (mcr & SP_UART_MCR_RI)
+		ret |= TIOCM_RI;
+
+	if (mcr & SP_UART_MCR_LB)
+		ret |= TIOCM_LOOP;
+
+	if (mcr & SP_UART_MCR_AC)
+		ret |= TIOCM_CTS;
+
+	return ret;
+}
+
+static void sunplus_stop_tx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = readl(port->membase + SP_UART_ISC);
+	isc &= ~SP_UART_ISC_TXM;
+	writel(isc, port->membase + SP_UART_ISC);
+}
+
+static inline void __start_tx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = readl(port->membase + SP_UART_ISC);
+	isc |= SP_UART_ISC_TXM;
+	writel(isc, port->membase + SP_UART_ISC);
+}
+
+static void sunplus_start_tx(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	ktime_t ktime;
+	int val;
+
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED) {
+		val = (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND ? 1 : 0);
+		if (!IS_ERR(sp_port->rts_gpio))
+			gpiod_set_value(sp_port->rts_gpio, val);
+
+		dev_dbg(port->dev, "%s set rts_gpio=%d\n", sp_port->uport.name, val);
+		if (sp_port->uport.rs485.delay_rts_before_send > 0) {
+			long nsec = sp_port->uport.rs485.delay_rts_before_send * 1000000;
+
+			ktime = ktime_set(0, nsec);
+			hrtimer_start(&sp_port->rts_delay_before_send, ktime, HRTIMER_MODE_REL);
+			return;
+		}
+	}
+	__start_tx(port);
+}
+
+static void sunplus_stop_rx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = readl(port->membase + SP_UART_ISC);
+	isc &= ~SP_UART_ISC_RXM;
+	writel(isc, port->membase + SP_UART_ISC);
+}
+
+static void sunplus_enable_ms(struct uart_port *port)
+{
+	/* Do nothing */
+}
+
+static void sunplus_break_ctl(struct uart_port *port, int ctl)
+{
+	unsigned long flags;
+	unsigned int lcr;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	lcr = readl(port->membase + SP_UART_LCR);
+
+	if (ctl != 0)
+		lcr |= SP_UART_LCR_BC;	/* start break */
+	else
+		lcr &= ~SP_UART_LCR_BC;	/* stop break */
+
+	writel(lcr, port->membase + SP_UART_LCR);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void transmit_chars(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	struct sunplus_dma_info *tx_dma = sp_port->uartdma_tx;
+	u32 tx_buf_available;
+	u32 addr_sw, addr_start;
+	u32 offset_sw;
+	u8 *byte_ptr;
+	struct circ_buf *xmit = &port->state->xmit;
+
+	if (port->x_char) {
+		sp_uart_put_char(port, port->x_char);
+		port->icount.tx++;
+		port->x_char = 0;
+		return;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+		sunplus_stop_tx(port);
+		return;
+	}
+
+	if (tx_dma) {
+		addr_sw = readl(tx_dma->membase + SP_UART_TXDMA_WR_ADR);
+		addr_start = readl(tx_dma->membase + SP_UART_TXDMA_START_ADDR);
+		offset_sw = addr_sw - addr_start;
+		byte_ptr = (u8 *)(tx_dma->buf_va + offset_sw);
+		tx_buf_available = sp_uart_line_status_tx_buf_not_full(port);
+		while (tx_buf_available) {
+			*byte_ptr = xmit->buf[xmit->tail];
+			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+			port->icount.tx++;
+
+			byte_ptr++;
+			addr_sw++;
+			offset_sw++;
+			tx_buf_available--;
+			if (offset_sw == PAGE_SIZE) {
+				offset_sw = 0;
+				addr_sw = (u32)(tx_dma->dma_handle);
+				byte_ptr = (u8 *)(tx_dma->buf_va);
+			}
+
+			if (uart_circ_empty(xmit))
+				break;
+		}
+		writel(addr_sw, tx_dma->membase + SP_UART_TXDMA_WR_ADR);
+	} else {
+		do {
+			sp_uart_put_char(port, xmit->buf[xmit->tail]);
+			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+			port->icount.tx++;
+
+			if (uart_circ_empty(xmit))
+				break;
+		} while (sp_uart_line_status_tx_buf_not_full(port));
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (uart_circ_empty(xmit))
+		sunplus_stop_tx(port);
+}
+
+/* called by ISR */
+static void receive_chars(struct uart_port *port)
+{
+	struct tty_struct *tty = port->state->port.tty;
+	unsigned int lsr = readl(port->membase + SP_UART_LSR);
+	unsigned int ch, flag;
+
+	do {
+		ch = readl(port->membase + SP_UART_DATA);
+
+		flag = TTY_NORMAL;
+		port->icount.rx++;
+
+		if (unlikely(lsr & SP_UART_LSR_BRK_ERROR_BITS)) {
+			if (port->cons == NULL)
+				dev_err(port->dev, "UART%d, SP_UART_LSR_BRK_ERROR_BITS, lsr = 0x%08X\n",
+					port->line, lsr);
+
+			if (lsr & SP_UART_LSR_BC) {
+				lsr &= ~(SP_UART_LSR_FE | SP_UART_LSR_PE);
+				port->icount.brk++;
+				if (uart_handle_break(port))
+					goto ignore_char;
+			} else if (lsr & SP_UART_LSR_PE) {
+				if (port->cons == NULL)
+					dev_err(port->dev, "UART%d, SP_UART_LSR_PE\n", port->line);
+				port->icount.parity++;
+			} else if (lsr & SP_UART_LSR_FE) {
+				if (port->cons == NULL)
+					dev_err(port->dev, "UART%d, SP_UART_LSR_FE\n", port->line);
+				port->icount.frame++;
+			}
+			if (lsr & SP_UART_LSR_OE) {
+				if (port->cons == NULL)
+					dev_err(port->dev, "UART%d, SP_UART_LSR_OE\n", port->line);
+				port->icount.overrun++;
+			}
+
+			/*
+			 * Mask off conditions which should be ignored.
+			 */
+
+			/* lsr &= port->read_status_mask; */
+
+			if (lsr & SP_UART_LSR_BC)
+				flag = TTY_BREAK;
+			else if (lsr & SP_UART_LSR_PE)
+				flag = TTY_PARITY;
+			else if (lsr & SP_UART_LSR_FE)
+				flag = TTY_FRAME;
+		}
+
+		if (port->ignore_status_mask & SP_UART_CREAD_DISABLED)
+			goto ignore_char;
+
+		if (uart_handle_sysrq_char(port, ch))
+			goto ignore_char;
+
+		uart_insert_char(port, lsr, SP_UART_LSR_OE, ch, flag);
+
+ignore_char:
+		lsr = readl(port->membase + SP_UART_LSR);
+	} while (lsr & SP_UART_LSR_RX);
+
+	if (tty) {
+		spin_unlock(&port->lock);
+		tty_flip_buffer_push(tty->port);
+		spin_lock(&port->lock);
+	}
+}
+
+static irqreturn_t sunplus_uart_irq(int irq, void *args)
+{
+	struct uart_port *port = (struct uart_port *)args;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	if (readl(port->membase + SP_UART_ISC) & SP_UART_ISC_RX)
+		receive_chars(port);
+
+	if (readl(port->membase + SP_UART_ISC) & SP_UART_ISC_TX)
+		transmit_chars(port);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+/* called by ISR */
+static void receive_chars_rxdma(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	struct sunplus_dma_info *rx_dma = sp_port->uartdma_rx;
+	struct tty_struct *tty = port->state->port.tty;
+	u32 offset_sw, offset_hw, rx_size, dma_start;
+	u8 *sw_ptr, *buf_end_ptr, *u8_ptr;
+	u32 icount_rx;
+	u32 tmp_u32, value;
+	u8 tmp_buf[32];
+	int i;
+
+	dma_start = readl(rx_dma->membase + SP_UART_RXDMA_START_ADDR);
+	offset_sw = readl(rx_dma->membase + SP_UART_RXDMA_RD_ADR) - dma_start;
+	offset_hw = readl(rx_dma->membase + SP_UART_RXDMA_WR_ADR) - dma_start;
+
+	if (offset_hw >= offset_sw)
+		rx_size = offset_hw - offset_sw;
+	else
+		rx_size = offset_hw + PAGE_SIZE - offset_sw;
+
+	sw_ptr = (u8 *)(rx_dma->buf_va + offset_sw);
+	buf_end_ptr = (u8 *)(rx_dma->buf_va + PAGE_SIZE);
+
+	/*
+	 * Retrieve all data in ISR.
+	 * The max. received size is (buffer_size - threshold_size)
+	 * = (rxdma_length_thr[31:16] - rxdma_length_thr[15:0])
+	 * In order to limit the execution time in this ISR:
+	 * => Increase rxdma_length_thr[15:0] to shorten each ISR execution time.
+	 * => Don't need to set a small threshold_size,
+	 *    and split a long ISR into several shorter ISRs.
+	 */
+	icount_rx = 0;
+	while (rx_size > icount_rx) {
+		/* 32-byte aligned */
+		if (!(((unsigned long)(sw_ptr)) & (32 - 1))
+		    && ((rx_size - icount_rx) >= 32)) {
+			/*
+			 * Copy 32 bytes data from non cache area to cache area.
+			 * => It should use less DRAM controller's read command.
+			 */
+			memcpy(tmp_buf, sw_ptr, 32);
+			u8_ptr = (u8 *)(tmp_buf);
+			for (i = 0; i < 32; i++) {
+				port->icount.rx++;
+				uart_insert_char(port, 0, SP_UART_LSR_OE,
+					(unsigned int)(*u8_ptr), TTY_NORMAL);
+				u8_ptr++;
+			}
+			sw_ptr += 32;
+			icount_rx += 32;
+		} else {
+			port->icount.rx++;
+			uart_insert_char(port, 0, SP_UART_LSR_OE,
+				(unsigned int)(*sw_ptr), TTY_NORMAL);
+			sw_ptr++;
+			icount_rx++;
+		}
+		if (sw_ptr >= buf_end_ptr)
+			sw_ptr = (u8 *)(rx_dma->buf_va);
+	}
+
+	tmp_u32 = readl(rx_dma->membase + SP_UART_RXDMA_RD_ADR) + rx_size;
+
+	if (tmp_u32 <= readl(rx_dma->membase + SP_UART_RXDMA_END_ADDR))
+		writel(tmp_u32, rx_dma->membase + SP_UART_RXDMA_RD_ADR);
+	else
+		writel((tmp_u32 - PAGE_SIZE), rx_dma->membase + SP_UART_RXDMA_RD_ADR);
+
+	spin_unlock(&port->lock);
+	tty_flip_buffer_push(tty->port);
+	spin_lock(&port->lock);
+
+	value = readl(rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+	value |= DMA_INT;
+	writel(value, rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+
+	value = readl(rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+	value |= DMA_GO;
+	writel(value, rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+
+}
+
+static irqreturn_t sunplus_uart_rxdma_irq(int irq, void *args)
+{
+	struct uart_port *port = (struct uart_port *)args;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	receive_chars_rxdma(port);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int sunplus_startup(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	struct sunplus_dma_info *rx_dma, *tx_dma;
+	u32 timeout, interrupt_en;
+	unsigned int ch, value;
+	int ret;
+
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED)
+		hrtimer_cancel(&sp_port->rts_delay_after_send);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (port->line > 0) {
+		ret = pm_runtime_get_sync(port->dev);
+		if (ret < 0)
+			goto out;
+	}
+#endif
+
+	ret = request_irq(port->irq, sunplus_uart_irq, 0, sp_port->name, port);
+	if (ret)
+		return ret;
+
+	rx_dma = sp_port->uartdma_rx;
+
+	if (rx_dma) {
+		if (rx_dma->buf_va == NULL) {
+			/* Drop data in Rx FIFO (PIO mode) */
+			while (readl(port->membase + SP_UART_LSR) & SP_UART_LSR_RX)
+				ch = readl(port->membase + SP_UART_DATA);
+
+			rx_dma->buf_va =
+				dma_alloc_coherent(port->dev, PAGE_SIZE,
+				&(rx_dma->dma_handle), GFP_KERNEL);
+			if (rx_dma->buf_va == NULL) {
+				dev_err(port->dev, "Can't allocation buffer for %s\n",
+					sp_port->name);
+				ret = -ENOMEM;
+				goto error_01;
+			}
+
+			writel((u32)(rx_dma->dma_handle),
+				rx_dma->membase + SP_UART_RXDMA_START_ADDR);
+			writel((u32)(rx_dma->dma_handle),
+				rx_dma->membase + SP_UART_RXDMA_RD_ADR);
+
+			/* Switch clock source when setting baud rate */
+			timeout = (sp_port->pllsys_rate / 2) / 1000;	/* 1 msec */
+			writel(timeout, rx_dma->membase + SP_UART_RXDMA_TIMEOUT_SET);
+
+			/*
+			 * When there are only rxdma_length_thr[15:0] bytes
+			 * of free buffer => Trigger interrupt
+			 */
+			writel((PAGE_SIZE << 16) | (PAGE_SIZE - (PAGE_SIZE >> 3)),
+			    rx_dma->membase + SP_UART_RXDMA_LENGTH_THR);
+
+			value = readl(rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+			value &= ~DMA_SEL_UARTX_MASK;
+			value |= (DMA_INIT | (rx_dma->which_uart << DMA_SEL_UARTX_SHIFT));
+			writel(value, rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+
+			value = readl(rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+			value &= ~DMA_INIT;
+			writel(value, rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+
+			value = readl(rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+			value |= (DMA_SW_RST_B | DMA_AUTO_ENABLE | DMA_TIMEOUT_INT_EN | DMA_ENABLE);
+			writel(value, rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+
+			value = readl(rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+			value |= DMA_GO;
+			writel(value, rx_dma->membase + SP_UART_RXDMA_ENABLE_SEL);
+		}
+
+		ret = request_irq(rx_dma->irq, sunplus_uart_rxdma_irq, 0, "UARTDMA_RX", port);
+		if (ret) {
+			dma_free_coherent(port->dev, PAGE_SIZE,
+				rx_dma->buf_va, rx_dma->dma_handle);
+			goto error_00;
+		}
+	}
+
+	tx_dma = sp_port->uartdma_tx;
+	if (tx_dma) {
+		if (tx_dma->buf_va == NULL) {
+			tx_dma->buf_va =
+				dma_alloc_coherent(port->dev, PAGE_SIZE,
+				&(tx_dma->dma_handle), GFP_KERNEL);
+			if (tx_dma->buf_va == NULL) {
+				dev_err(port->dev, "Can't allocation buffer for %s\n",
+					sp_port->name);
+				ret = -ENOMEM;
+				goto error_01;
+			}
+
+			/*
+			 * set 1ms , set wr_adr , set start_addr/end_addr ,
+			 * set bind to uart# , set int enable ,
+			 * set txdma enable (Use ring buffer for UART's Tx)
+			 */
+			writel((sp_port->pllsys_rate / 1000),
+				tx_dma->membase + SP_UART_TXDMA_TMR_UNIT);
+			writel((u32)(tx_dma->dma_handle), tx_dma->membase + SP_UART_TXDMA_WR_ADR);
+			writel((u32)(tx_dma->dma_handle),
+				tx_dma->membase + SP_UART_TXDMA_START_ADDR);
+			writel(((u32)(tx_dma->dma_handle) + PAGE_SIZE - 1),
+				tx_dma->membase + SP_UART_TXDMA_END_ADDR);
+			writel(tx_dma->which_uart, tx_dma->membase + SP_UART_TXDMA_SEL);
+			writel(0x41, tx_dma->gdma_membase + SP_UART_TXGDMA_INT_EN);
+			writel(0x00000005, tx_dma->membase + SP_UART_TXDMA_ENABLE);
+		}
+	}
+
+	/*
+	 * don't need to use spin_lock_irqsave() because interrupts
+	 * are globally disabled
+	 */
+	spin_lock_irq(&port->lock);
+
+	/* SP_UART_ISC_TXM is enabled in .start_tx() */
+	interrupt_en = 0;
+	if (rx_dma == NULL)
+		interrupt_en |= SP_UART_ISC_RXM;
+
+	writel(interrupt_en, port->membase + SP_UART_ISC);
+
+	spin_unlock_irq(&port->lock);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (port->line > 0)
+		pm_runtime_put(port->dev);
+
+	return 0;
+
+out:
+	if (port->line > 0) {
+		pm_runtime_mark_last_busy(port->dev);
+		pm_runtime_put_autosuspend(port->dev);
+	}
+#endif
+	return 0;
+
+error_01:
+	if (rx_dma) {
+		dma_free_coherent(port->dev, PAGE_SIZE,
+			rx_dma->buf_va, rx_dma->dma_handle);
+		free_irq(rx_dma->irq, port);
+	}
+error_00:
+	free_irq(port->irq, port);
+	return ret;
+}
+
+static void sunplus_shutdown(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	struct sunplus_dma_info *rx_dma;
+	unsigned int mcr, value;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	writel(0, port->membase + SP_UART_ISC);
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	free_irq(port->irq, port);
+
+	rx_dma = sp_port->uartdma_rx;
+	if (rx_dma) {
+		/* Drop whatever is still in buffer */
+		value = readl(rx_dma->membase + SP_UART_RXDMA_WR_ADR);
+		writel(value, rx_dma->membase + SP_UART_RXDMA_RD_ADR);
+
+		free_irq(rx_dma->irq, port);
+	}
+
+	/* Disable flow control of Tx, so that queued data can be sent out
+	 * There is no way for s/w to let h/w abort in the middle of
+	 * transaction.
+	 * Don't reset module except it's in idle state. Otherwise, it might
+	 * cause bus to hang.
+	 */
+	mcr = readl(port->membase + SP_UART_MCR);
+	mcr &= ~SP_UART_MCR_AC;
+	writel(mcr, port->membase + SP_UART_MCR);
+
+}
+
+static void sunplus_set_termios(struct uart_port *port,
+	struct ktermios *termios, struct ktermios *oldtermios)
+{
+	u32 clk, ext, div, div_l, div_h, baud;
+	u32 lcr, mcr;
+	unsigned long flags;
+
+	clk = port->uartclk;
+
+	baud = uart_get_baud_rate(port, termios, oldtermios, 0, port->uartclk / 16);
+
+	/*
+	 * Send all data in Tx FIFO before changing clock source,
+	 * it should be UART0 only
+	 */
+	while (!(readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TXE))
+		;
+
+	clk += baud >> 1;
+	div = clk / baud;
+	ext = div & 0x0F;
+	div = (div >> 4) - 1;
+	div_l = (div & 0xFF) | (ext << 12);
+	div_h = div >> 8;
+
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		lcr = SP_UART_LCR_WL5;
+		break;
+	case CS6:
+		lcr = SP_UART_LCR_WL6;
+		break;
+	case CS7:
+		lcr = SP_UART_LCR_WL7;
+		break;
+	default:	/* CS8 */
+		lcr = SP_UART_LCR_WL8;
+		break;
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		lcr |= SP_UART_LCR_ST;
+
+	if (termios->c_cflag & PARENB) {
+		lcr |= SP_UART_LCR_PE;
+
+		if (!(termios->c_cflag & PARODD))
+			lcr |= SP_UART_LCR_PR;
+	}
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	port->read_status_mask = 0;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= SP_UART_LSR_PE | SP_UART_LSR_FE;
+
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		port->read_status_mask |= SP_UART_LSR_BC;
+
+	/*
+	 * Characters to ignore
+	 */
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= SP_UART_LSR_FE | SP_UART_LSR_PE;
+
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= SP_UART_LSR_BC;
+
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= SP_UART_LSR_OE;
+	}
+
+	/*
+	 * Ignore all characters if CREAD is not set.
+	 */
+	if ((termios->c_cflag & CREAD) == 0) {
+		port->ignore_status_mask |= SP_UART_CREAD_DISABLED;
+		/* flush rx data FIFO */
+		writel(0, port->membase + SP_UART_RX_RESIDUE);
+	}
+
+	mcr = readl(port->membase + SP_UART_MCR);
+
+	if (termios->c_cflag & CRTSCTS)
+		mcr |= (SP_UART_MCR_AC | SP_UART_MCR_AR);
+	else
+		mcr &= ~(SP_UART_MCR_AC | SP_UART_MCR_AR);
+
+	writel(mcr, port->membase + SP_UART_MCR);
+
+	/* do not set these in emulation */
+	writel(div_h, port->membase + SP_UART_DIV_H);
+	writel(div_l, port->membase + SP_UART_DIV_L);
+	writel(lcr, port->membase + SP_UART_LCR);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void sunplus_set_ldisc(struct uart_port *port,
+				       struct ktermios *termios)
+{
+	int new = termios->c_line;
+
+	if (new == N_PPS) {
+		port->flags |= UPF_HARDPPS_CD;
+		sunplus_enable_ms(port);
+	} else {
+		port->flags &= ~UPF_HARDPPS_CD;
+	}
+}
+
+static const char *sunplus_type(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+
+	return sp_port->name;
+}
+
+static void sunplus_release_port(struct uart_port *port)
+{
+}
+
+static int sunplus_request_port(struct uart_port *port)
+{
+	return 0;
+}
+
+static void sunplus_config_port(struct uart_port *port, int type)
+{
+	if (type & UART_CONFIG_TYPE) {
+		port->type = PORT_SUNPLUS;
+		sunplus_request_port(port);
+	}
+}
+
+static int sunplus_verify_port(struct uart_port *port, struct serial_struct *serial)
+{
+	return -EINVAL;
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+static int sunplus_poll_init(struct uart_port *port)
+{
+	return 0;
+}
+
+static void sunplus_poll_put_char(struct uart_port *port, unsigned char data)
+{
+	wait_for_xmitr(port);
+	sp_uart_put_char(port, data);
+}
+
+static int sunplus_poll_get_char(struct uart_port *port)
+{
+	unsigned int lsr;
+
+	do {
+		lsr = readl(port->membase + SP_UART_LSR);
+	} while (!(lsr & SP_UART_LSR_RX));
+
+	return readl(port->membase + SP_UART_DATA);
+}
+#endif /* CONFIG_CONSOLE_POLL */
+
+static enum hrtimer_restart sp_rts_check_tx_empty(struct hrtimer *t)
+{
+	struct sunplus_uart_port *sp_port;
+	unsigned int mcr, lsr;
+	unsigned char val;
+	ktime_t ktime;
+	unsigned long nsec;
+
+	sp_port = container_of(t, struct sunplus_uart_port, rts_check_tx_empty);
+	mcr = readl(sp_port->uport.membase + SP_UART_MCR);
+	lsr = readl(sp_port->uport.membase + SP_UART_LSR);
+	// TX is NOT empty
+	if (!(lsr & SP_UART_LSR_TXE))
+		return HRTIMER_RESTART;
+	// TX is empty
+	nsec = sp_port->uport.rs485.delay_rts_after_send * 1000000;
+	// schedule RTS set
+	if (nsec > 0) {
+		ktime = ktime_set(0, nsec);
+		hrtimer_start(&sp_port->rts_delay_after_send, ktime, HRTIMER_MODE_REL);
+		return HRTIMER_NORESTART;
+	}
+	// immediately set RTS
+	val = (sp_port->uport.rs485.flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0);
+	if (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND)
+		mcr |= SP_UART_MCR_RTS;
+	else
+		mcr &= ~SP_UART_MCR_RTS;
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED && !IS_ERR(sp_port->rts_gpio)) {
+		gpiod_set_value(sp_port->rts_gpio, val);
+		dev_dbg(sp_port->uport.dev, "%s set rts_gpio=%d\n",
+			sp_port->uport.name, val);
+	} else
+		writel(mcr, sp_port->uport.membase + SP_UART_MCR);
+
+	return HRTIMER_NORESTART;
+}
+
+static enum hrtimer_restart sp_rts_delay_before_send(struct hrtimer *t)
+{
+	struct sunplus_uart_port *sp_port;
+	ktime_t ktime;
+
+	sp_port = container_of(t, struct sunplus_uart_port, rts_delay_before_send);
+	ktime = ktime_set(0, 500000); //500us
+	hrtimer_start(&sp_port->rts_check_tx_empty, ktime, HRTIMER_MODE_REL);
+	__start_tx(&sp_port->uport);
+	return HRTIMER_NORESTART;
+}
+
+static enum hrtimer_restart sp_rts_delay_after_send(struct hrtimer *t)
+{
+	struct sunplus_uart_port *sp_port;
+	unsigned char val;
+	unsigned int mcr;
+
+	sp_port = container_of(t, struct sunplus_uart_port, rts_delay_after_send);
+	mcr = readl(sp_port->uport.membase + SP_UART_MCR);
+
+	val = (sp_port->uport.rs485.flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0);
+	if (sp_port->uport.rs485.flags & SER_RS485_RTS_ON_SEND)
+		mcr |= SP_UART_MCR_RTS;
+	else
+		mcr &= ~SP_UART_MCR_RTS;
+	if (sp_port->uport.rs485.flags & SER_RS485_ENABLED && !IS_ERR(sp_port->rts_gpio)) {
+		gpiod_set_value(sp_port->rts_gpio, val);
+		dev_dbg(sp_port->uport.dev, "%s set rts_gpio=%d\n",
+			sp_port->uport.name, val);
+	} else
+		writel(mcr, sp_port->uport.membase + SP_UART_MCR);
+
+	return HRTIMER_NORESTART;
+}
+
+static int sunplus_uart_rs485_on(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+
+	if (IS_ERR(sp_port->rts_gpio)) {
+		dev_err(port->dev, "%s No valid rts_gpio, disabling 485\n",
+			port->name);
+		port->rs485.flags &= ~SER_RS485_ENABLED;
+		return (-EINVAL);
+	}
+
+	if (!sp_port->rts_check_tx_empty.function) {
+		hrtimer_init(&(sp_port->rts_check_tx_empty), CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		sp_port->rts_check_tx_empty.function = sp_rts_check_tx_empty;
+	}
+	if (!sp_port->rts_delay_before_send.function) {
+		hrtimer_init(&(sp_port->rts_delay_before_send), CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		sp_port->rts_delay_before_send.function = sp_rts_delay_before_send;
+	}
+	if (!sp_port->rts_delay_after_send.function) {
+		hrtimer_init(&(sp_port->rts_delay_after_send), CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		sp_port->rts_delay_after_send.function = sp_rts_delay_after_send;
+	}
+	return (0);
+}
+
+static int sunplus_uart_rs485_off(struct uart_port *port)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+
+	port->rs485.flags &= ~SER_RS485_ENABLED;
+	if (sp_port->rts_check_tx_empty.function) {
+		hrtimer_cancel(&sp_port->rts_check_tx_empty);
+		sp_port->rts_check_tx_empty.function = NULL;
+	}
+	if (sp_port->rts_delay_before_send.function) {
+		hrtimer_cancel(&sp_port->rts_delay_before_send);
+		sp_port->rts_delay_before_send.function = NULL;
+	}
+	if (sp_port->rts_delay_after_send.function) {
+		hrtimer_cancel(&sp_port->rts_delay_after_send);
+		sp_port->rts_delay_after_send.function = NULL;
+	}
+	return (0);
+}
+
+static int sunplus_uart_config_rs485(struct uart_port *port,
+	struct serial_rs485 *rs485)
+{
+	struct sunplus_uart_port *sp_port = to_sunplus_uart(port);
+	int val;
+
+	if (IS_ERR(sp_port->rts_gpio)) {
+		dev_err(port->dev, "%s No valid rts_gpio - skipping rs485\n",
+			port->name);
+		port->rs485.flags &= ~SER_RS485_ENABLED;
+		return (-EINVAL);
+	}
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	pm_runtime_get_sync(sp_port->dev);
+#endif
+
+	rs485->delay_rts_before_send =
+		min(rs485->delay_rts_before_send, 10000U);
+	rs485->delay_rts_after_send  =
+		min(rs485->delay_rts_after_send, 10000U);
+
+	if (rs485->flags & SER_RS485_ENABLED) {
+		sunplus_uart_rs485_on(port);
+		val = (rs485->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0);
+		gpiod_set_value(sp_port->rts_gpio, val);
+	} else
+		sunplus_uart_rs485_off(port);
+
+	port->rs485 = *rs485;
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	pm_runtime_mark_last_busy(sp_port->dev);
+	pm_runtime_put_autosuspend(sp_port->dev);
+#endif
+	return (0);
+}
+
+static const struct uart_ops sunplus_uart_ops = {
+	.tx_empty		= sunplus_tx_empty,
+	.set_mctrl		= sunplus_set_mctrl,
+	.get_mctrl		= sunplus_get_mctrl,
+	.stop_tx		= sunplus_stop_tx,
+	.start_tx		= sunplus_start_tx,
+	.stop_rx		= sunplus_stop_rx,
+	.enable_ms		= sunplus_enable_ms,
+	.break_ctl		= sunplus_break_ctl,
+	.startup		= sunplus_startup,
+	.shutdown		= sunplus_shutdown,
+	.set_termios	= sunplus_set_termios,
+	.set_ldisc		= sunplus_set_ldisc,
+	.type			= sunplus_type,
+	.release_port	= sunplus_release_port,
+	.request_port	= sunplus_request_port,
+	.config_port	= sunplus_config_port,
+	.verify_port	= sunplus_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+	.poll_init		= sunplus_poll_init,
+	.poll_put_char	= sunplus_poll_put_char,
+	.poll_get_char	= sunplus_poll_get_char,
+#endif /* CONFIG_CONSOLE_POLL */
+};
+
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+static void sunplus_uart_console_putchar(struct uart_port *port, int ch)
+{
+	wait_for_xmitr(port);
+	sp_uart_put_char(port, ch);
+}
+
+static void sunplus_console_write(struct console *co,
+	const char *s, unsigned int count)
+{
+	unsigned long flags;
+	int locked = 1;
+
+	local_irq_save(flags);
+
+	if (sunplus_uart_ports[co->index].uport.sysrq)
+		locked = 0;
+	else if (oops_in_progress)
+		locked = spin_trylock(&sunplus_uart_ports[co->index].uport.lock);
+	else
+		spin_lock(&sunplus_uart_ports[co->index].uport.lock);
+
+	uart_console_write(&sunplus_uart_ports[co->index].uport,
+		s, count, sunplus_uart_console_putchar);
+
+	if (locked)
+		spin_unlock(&sunplus_uart_ports[co->index].uport.lock);
+
+	local_irq_restore(flags);
+}
+
+static int __init sunplus_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	if ((co->index >= UART_NR) || (co->index < 0))
+		return -EINVAL;
+
+	port = &sunplus_uart_ports[co->index].uport;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console sunplus_console = {
+	.name		= "ttyS",
+	.write		= sunplus_console_write,
+	.device		= uart_console_device,
+	.setup		= sunplus_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &sunplus_uart_driver
+};
+#endif
+
+static struct uart_driver sunplus_uart_driver = {
+	.owner		= THIS_MODULE,
+	.driver_name	= "Sunplus_UART",
+	.dev_name	= "ttyS",
+	.major		= TTY_MAJOR,
+	.minor		= 64,
+	.nr			= UART_NR,
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+	.cons		= &sunplus_console
+#endif
+};
+
+static int sunplus_uart_probe(struct platform_device *pdev)
+{
+	struct resource *res_mem;
+	struct uart_port *port;
+	struct clk *clk, *pllsys;
+	unsigned int pllsys_rate;
+	int ret, irq;
+	int idx_offset, idx;
+	int idx_which_uart;
+	char peri_name[16];
+
+	if (pdev->dev.of_node) {
+		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
+		if (pdev->id < 0)
+			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
+	}
+
+	idx_offset = -1;
+
+	if (IS_UARTDMARX_ID(pdev->id))
+		idx_offset = 0;
+	else if (IS_UARTDMATX_ID(pdev->id))
+		idx_offset = UART_DMARX_NR;
+
+	/* init txdma or rxdma */
+	if (idx_offset >= 0) {
+		clk = devm_clk_get(&pdev->dev, NULL);
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+
+		ret = clk_prepare_enable(clk);
+		if (ret)
+			return ret;
+
+		if (idx_offset == 0)
+			idx = idx_offset + pdev->id - ID_BASE_DMARX;
+		else
+			idx = idx_offset + pdev->id - ID_BASE_DMATX;
+
+		res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res_mem)
+			return -ENODEV;
+
+		sprintf(peri_name, "PERI%d", (idx & 0x01));
+
+		clk = devm_clk_get(&pdev->dev, peri_name);
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+
+		ret = clk_prepare_enable(clk);
+		if (ret)
+			return ret;
+
+		sunplus_uartdma[idx].addr_phy =
+			(unsigned long)(res_mem->start);
+		sunplus_uartdma[idx].membase =
+			devm_ioremap_resource(&pdev->dev, res_mem);
+
+		if (IS_ERR(sunplus_uartdma[idx].membase))
+			return PTR_ERR(sunplus_uartdma[idx].membase);
+
+		if (IS_UARTDMARX_ID(pdev->id)) {
+			irq = platform_get_irq(pdev, 0);
+			if (irq < 0)
+				return -ENODEV;
+
+			sunplus_uartdma[idx].irq = irq;
+		} else {
+			res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+			if (!res_mem)
+				return -ENODEV;
+
+			sunplus_uartdma[idx].gdma_membase =
+				devm_ioremap_resource(&pdev->dev, res_mem);
+
+			if (IS_ERR(sunplus_uartdma[idx].gdma_membase))
+				return -EINVAL;
+		}
+
+		if (of_property_read_u32(pdev->dev.of_node, "which-uart", &idx_which_uart) != 0) {
+			dev_err(&pdev->dev, "\"which-uart\" is not assigned.");
+			return -EINVAL;
+		}
+
+		if (idx_which_uart >= UART_NR) {
+			dev_err(&pdev->dev, "\"which-uart\" is not valid.");
+			return -EINVAL;
+		}
+
+		sunplus_uartdma[idx].which_uart = idx_which_uart;
+
+		return 0;
+	} else if (pdev->id < 0 || pdev->id >= UART_NR)
+		return -EINVAL;
+
+	/* init uart */
+	port = &sunplus_uart_ports[pdev->id].uport;
+	if (port->membase)
+		return -EBUSY;
+
+	memset(port, 0, sizeof(*port));
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_mem)
+		return -ENODEV;
+
+	port->dev = &pdev->dev;
+	port->mapbase = res_mem->start;
+
+	port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
+	if (IS_ERR(port->membase))
+		return PTR_ERR(port->membase);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -ENODEV;
+
+	uart_get_rs485_mode(port);
+	sunplus_uart_ports[pdev->id].rts_gpio =
+		devm_gpiod_get(&pdev->dev, "rts", GPIOD_OUT_LOW);
+	port->rs485_config = sunplus_uart_config_rs485;
+	sunplus_uart_ports[pdev->id].rts_check_tx_empty.function = NULL;
+	sunplus_uart_ports[pdev->id].rts_delay_before_send.function = NULL;
+	sunplus_uart_ports[pdev->id].rts_delay_after_send.function = NULL;
+	if (port->rs485.flags & SER_RS485_ENABLED)
+		sunplus_uart_rs485_on(port);
+
+	sunplus_uart_ports[pdev->id].clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(sunplus_uart_ports[pdev->id].clk))
+		return PTR_ERR(sunplus_uart_ports[pdev->id].clk);
+
+	ret = clk_prepare_enable(sunplus_uart_ports[pdev->id].clk);
+	if (ret)
+		return ret;
+
+	sunplus_uart_ports[pdev->id].rstc =
+		devm_reset_control_get(&pdev->dev, NULL);
+
+	if (IS_ERR(sunplus_uart_ports[pdev->id].rstc))
+		return PTR_ERR(sunplus_uart_ports[pdev->id].rstc);
+
+	ret = reset_control_deassert(sunplus_uart_ports[pdev->id].rstc);
+	if (ret)
+		return ret;
+
+	clk = sunplus_uart_ports[pdev->id].clk;
+	if (IS_ERR(clk))
+		port->uartclk = XTAL;
+	else
+		port->uartclk = clk_get_rate(clk);
+
+	pllsys = clk_get_sys("pllsys", NULL);
+	pllsys_rate = clk_get_rate(pllsys);
+
+	sunplus_uart_ports[pdev->id].pllsys_rate = pllsys_rate;
+
+	port->iotype = UPIO_MEM;
+	port->irq = irq;
+	port->ops = &sunplus_uart_ops;
+	port->flags = UPF_BOOT_AUTOCONF;
+	port->fifosize = 128;
+	port->line = pdev->id;
+
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+	if (pdev->id == 0)
+		port->cons = &sunplus_console;
+#endif
+
+	port->private_data = container_of(&sunplus_uart_ports[pdev->id].uport,
+		struct sunplus_uart_port, uport);
+
+	sprintf(sunplus_uart_ports[pdev->id].name, "sp_uart%d", pdev->id);
+
+	sunplus_uart_ports[pdev->id].uartdma_rx =
+		sunplus_uartdma_rx_binding(pdev->id);
+
+	if (sunplus_uart_ports[pdev->id].uartdma_rx)
+		dev_info(port->dev, "%s's Rx is in DMA mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+	else
+		dev_info(port->dev, "%s's Rx is in PIO mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+
+	sunplus_uart_ports[pdev->id].uartdma_tx =
+		sunplus_uartdma_tx_binding(pdev->id);
+
+	if (sunplus_uart_ports[pdev->id].uartdma_tx)
+		dev_info(port->dev, "%s's Tx is in DMA mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+	else
+		dev_info(port->dev, "%s's Tx is in PIO mode.\n",
+			sunplus_uart_ports[pdev->id].name);
+
+	ret = uart_add_one_port(&sunplus_uart_driver, port);
+	if (ret) {
+		port->membase = NULL;
+		return ret;
+	}
+	platform_set_drvdata(pdev, port);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (pdev->id != 0) {
+		pm_runtime_set_autosuspend_delay(&pdev->dev, 5000);
+		pm_runtime_use_autosuspend(&pdev->dev);
+		pm_runtime_set_active(&pdev->dev);
+		pm_runtime_enable(&pdev->dev);
+	}
+#endif
+	return 0;
+}
+
+static int sunplus_uart_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (pdev->id != 0) {
+		pm_runtime_disable(&pdev->dev);
+		pm_runtime_set_suspended(&pdev->dev);
+	}
+#endif
+	uart_remove_one_port(&sunplus_uart_driver,
+		&sunplus_uart_ports[pdev->id].uport);
+
+	if (pdev->id < UART_NR) {
+		clk_disable_unprepare(sunplus_uart_ports[pdev->id].clk);
+		reset_control_assert(sunplus_uart_ports[pdev->id].rstc);
+	}
+
+	return 0;
+}
+
+static int sunplus_uart_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	/* Don't suspend uart0 for cmd line usage */
+	if ((pdev->id < UART_NR) && (pdev->id > 0))
+		reset_control_assert(sunplus_uart_ports[pdev->id].rstc);
+
+	return 0;
+}
+
+static int sunplus_uart_resume(struct platform_device *pdev)
+{
+	if (pdev->id < UART_NR) {
+		clk_prepare_enable(sunplus_uart_ports[pdev->id].clk);
+		reset_control_deassert(sunplus_uart_ports[pdev->id].rstc);
+	}
+	return 0;
+}
+
+static const struct of_device_id sp_uart_of_match[] = {
+	{ .compatible = "sunplus,sp7021-uart" },
+	{ .compatible = "sunplus,sp7021-uart-rxdma" },
+	{ .compatible = "sunplus,sp7021-uart-txdma" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sp_uart_of_match);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+static int sunplus_uart_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	/* Don't suspend uart0 for cmd line usage */
+	if ((pdev->id < UART_NR) && (pdev->id > 0))
+		reset_control_assert(sunplus_uart_ports[pdev->id].rstc);
+
+	return 0;
+}
+
+static int sunplus_uart_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	if (pdev->id < UART_NR) {
+		clk_prepare_enable(sunplus_uart_ports[pdev->id].clk);
+		reset_control_deassert(sunplus_uart_ports[pdev->id].rstc);
+	}
+
+	return 0;
+}
+static const struct dev_pm_ops sp7021_uart_pm_ops = {
+	.runtime_suspend = sunplus_uart_runtime_suspend,
+	.runtime_resume  = sunplus_uart_runtime_resume,
+};
+#define sunplus_uart_pm_ops  (&sp7021_uart_pm_ops)
+#endif
+
+static struct platform_driver sunplus_uart_platform_driver = {
+	.probe		= sunplus_uart_probe,
+	.remove		= sunplus_uart_remove,
+	.suspend	= sunplus_uart_suspend,
+	.resume		= sunplus_uart_resume,
+	.driver = {
+		.name	= "sunplus-uart",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(sp_uart_of_match),
+#ifdef CONFIG_PM_RUNTIME_UART
+		.pm     = sunplus_uart_pm_ops,
+#endif
+	}
+};
+
+static int __init sunplus_uart_init(void)
+{
+	int ret;
+
+	memset(sunplus_uart_ports, 0, sizeof(sunplus_uart_ports));
+	memset(sunplus_uartdma, 0, sizeof(sunplus_uartdma));
+
+	if (!uart0_as_console || !(uart_enable_status & 0x01))
+		sunplus_uart_driver.cons = NULL;
+
+	/* /proc/tty/driver/(sunplus_uart_driver->driver_name) */
+	ret = uart_register_driver(&sunplus_uart_driver);
+	if (ret < 0)
+		return ret;
+
+	ret = platform_driver_register(&sunplus_uart_platform_driver);
+	if (ret != 0) {
+		uart_unregister_driver(&sunplus_uart_driver);
+		return ret;
+	}
+
+	return 0;
+}
+module_init(sunplus_uart_init);
+
+module_param(uart0_as_console, uint, 0444);
+
+#ifdef CONFIG_SERIAL_EARLYCON
+static void sunplus_uart_putc(struct uart_port *port, int c)
+{
+	unsigned int status;
+
+	for (;;) {
+		status = readl(port->membase + SP_UART_LSR);
+		if ((status & SP_UART_LSR_TXE) == SP_UART_LSR_TXE)
+			break;
+		cpu_relax();
+	}
+	writel(c, port->membase + SP_UART_DATA);
+}
+
+static void sunplus_uart_early_write(struct console *con,
+			      const char *s, unsigned int n)
+{
+	struct earlycon_device *dev = con->data;
+
+	uart_console_write(&dev->port, s, n, sunplus_uart_putc);
+}
+
+int __init sunplus_uart_early_setup(struct earlycon_device *device,
+					 const char *opt)
+{
+	if (!(device->port.membase || device->port.iobase))
+		return -ENODEV;
+
+	device->con->write = sunplus_uart_early_write;
+	return 0;
+}
+OF_EARLYCON_DECLARE(sunplus_uart, "sunplus,sp7021-uart", sunplus_uart_early_setup);
+#endif
+
+MODULE_DESCRIPTION("Sunplus UART driver");
+MODULE_AUTHOR("Hammer Hsieh <hammer.hsieh@sunplus.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/soc/sunplus/sp_uart.h b/include/soc/sunplus/sp_uart.h
new file mode 100644
index 0000000..44bc1fb
--- /dev/null
+++ b/include/soc/sunplus/sp_uart.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Sunplus SoC UART driver header file
+ */
+
+#ifndef __SP_UART_H__
+#define __SP_UART_H__
+
+#ifdef CONFIG_DEBUG_SP_UART
+#include <mach/io_map.h>
+
+#define LL_UART_PADDR		PA_IOB_ADDR(18 * 32 * 4)
+#define LL_UART_VADDR		VA_IOB_ADDR(18 * 32 * 4)
+#define LOGI_ADDR_UART0_REG	VA_IOB_ADDR(18 * 32 * 4)
+#endif
+
+/*
+ * UART REG
+ *
+ */
+#define SP_UART_DATA			0x00
+#define SP_UART_LSR				0x04
+#define SP_UART_MSR				0x08
+#define SP_UART_LCR				0x0C
+#define SP_UART_MCR				0x10
+#define SP_UART_DIV_L			0x14
+#define SP_UART_DIV_H			0x18
+#define SP_UART_ISC				0x1C
+#define SP_UART_TX_RESIDUE		0x20
+#define SP_UART_RX_RESIDUE		0x24
+
+/* lsr
+ * 1: trasmit fifo is empty
+ */
+#define SP_UART_LSR_TXE		(1 << 6)
+
+/* interrupt
+ * SP_UART_LSR_BC : break condition
+ * SP_UART_LSR_FE : frame error
+ * SP_UART_LSR_OE : overrun error
+ * SP_UART_LSR_PE : parity error
+ * SP_UART_LSR_RX : 1: receive fifo not empty
+ * SP_UART_LSR_TX : 1: transmit fifo is not full
+ */
+#define SP_UART_CREAD_DISABLED		(1 << 16)
+#define SP_UART_LSR_BC		(1 << 5)
+#define SP_UART_LSR_FE		(1 << 4)
+#define SP_UART_LSR_OE		(1 << 3)
+#define SP_UART_LSR_PE		(1 << 2)
+#define SP_UART_LSR_RX		(1 << 1)
+#define SP_UART_LSR_TX		(1 << 0)
+
+#define SP_UART_LSR_BRK_ERROR_BITS	\
+	(SP_UART_LSR_PE | SP_UART_LSR_OE | SP_UART_LSR_FE | SP_UART_LSR_BC)
+
+/* lcr */
+#define SP_UART_LCR_WL5		(0 << 0)
+#define SP_UART_LCR_WL6		(1 << 0)
+#define SP_UART_LCR_WL7		(2 << 0)
+#define SP_UART_LCR_WL8		(3 << 0)
+#define SP_UART_LCR_ST		(1 << 2)
+#define SP_UART_LCR_PE		(1 << 3)
+#define SP_UART_LCR_PR		(1 << 4)
+#define SP_UART_LCR_BC		(1 << 5)
+
+/* isc
+ * SP_UART_ISC_MSM : Modem status ctrl
+ * SP_UART_ISC_LSM : Line status interrupt
+ * SP_UART_ISC_RXM : RX interrupt, when got some input data
+ * SP_UART_ISC_TXM : TX interrupt, when trans start
+ */
+#define SP_UART_ISC_MSM		(1 << 7)
+#define SP_UART_ISC_LSM		(1 << 6)
+#define SP_UART_ISC_RXM		(1 << 5)
+#define SP_UART_ISC_TXM		(1 << 4)
+#define HAS_UART_ISC_FLAGMASK	0x0F
+#define SP_UART_ISC_MS		(1 << 3)
+#define SP_UART_ISC_LS		(1 << 2)
+#define SP_UART_ISC_RX		(1 << 1)
+#define SP_UART_ISC_TX		(1 << 0)
+
+/* modem control register */
+#define SP_UART_MCR_AT		(1 << 7)
+#define SP_UART_MCR_AC		(1 << 6)
+#define SP_UART_MCR_AR		(1 << 5)
+#define SP_UART_MCR_LB		(1 << 4)
+#define SP_UART_MCR_RI		(1 << 3)
+#define SP_UART_MCR_DCD		(1 << 2)
+#define SP_UART_MCR_RTS		(1 << 1)
+#define SP_UART_MCR_DTS		(1 << 0)
+
+/*
+ * RX DMA REG
+ *
+ */
+#define SP_UART_RXDMA_ENABLE_SEL		0x00
+#define DMA_INT				(1 << 31)
+#define DMA_MSI_ID_SHIFT	12
+#define DMA_MSI_ID_MASK		(0x7F << DMA_MSI_ID_SHIFT)
+#define DMA_SEL_UARTX_SHIFT	8
+#define DMA_SEL_UARTX_MASK	(0x07 << DMA_SEL_UARTX_SHIFT)
+#define DMA_SW_RST_B		(1 << 7)
+#define DMA_INIT			(1 << 6)
+#define DMA_GO				(1 << 5)
+#define DMA_AUTO_ENABLE		(1 << 4)
+#define DMA_TIMEOUT_INT_EN	(1 << 3)
+#define DMA_P_SAFE_DISABLE	(1 << 2)
+#define DMA_PBUS_DATA_SWAP	(1 << 1)
+#define DMA_ENABLE			(1 << 0)
+#define SP_UART_RXDMA_START_ADDR		0x04
+#define SP_UART_RXDMA_TIMEOUT_SET		0x08
+#define SP_UART_RXDMA_WR_ADR			0x10
+#define SP_UART_RXDMA_RD_ADR			0x14
+#define SP_UART_RXDMA_LENGTH_THR		0x18
+#define SP_UART_RXDMA_END_ADDR			0x1C
+#define SP_UART_RXDMA_DATABYTES			0x20
+#define SP_UART_RXDMA_DEBUG_INFO		0x24
+/*
+ * TX DMA REG
+ *
+ */
+#define SP_UART_TXDMA_ENABLE			0x00
+#define SP_UART_TXDMA_SEL				0x04
+#define SP_UART_TXDMA_START_ADDR		0x08
+#define SP_UART_TXDMA_END_ADDR			0x0C
+#define SP_UART_TXDMA_WR_ADR			0x10
+#define SP_UART_TXDMA_RD_ADR			0x14
+#define SP_UART_TXDMA_STATUS			0x18
+#define TXDMA_BUF_FULL	0x01
+#define TXDMA_BUF_EMPTY	0x02
+#define SP_UART_TXDMA_TMR_UNIT			0x1C
+#define SP_UART_TXDMA_TMR_CNT			0x20
+#define SP_UART_TXDMA_RST_DONE			0x24
+/*
+ * TX GDMA REG
+ *
+ */
+#define SP_UART_TXGDMA_HW_VER			0x00
+#define SP_UART_TXGDMA_CONFIG			0x04
+#define SP_UART_TXGDMA_LENGTH			0x08
+#define SP_UART_TXGDMA_ADDR				0x0C
+#define SP_UART_TXGDMA_PORT_MUX			0x10
+#define SP_UART_TXGDMA_INT_FLAG			0x14
+#define SP_UART_TXGDMA_INT_EN			0x18
+#define SP_UART_TXGDMA_SOFT_RESET_STATUS	0x1C
+
+#endif /* __SP_UART_H__ */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-10  7:51   ` [PATCH v2 2/2] serial:sunplus-uart:Add " Hammer Hsieh
@ 2021-11-10  9:50     ` Philipp Zabel
  2021-11-11  9:45       ` Hammer Hsieh 謝宏孟
  2021-11-12  8:31     ` kernel test robot
  1 sibling, 1 reply; 19+ messages in thread
From: Philipp Zabel @ 2021-11-10  9:50 UTC (permalink / raw)
  To: Hammer Hsieh, gregkh, robh+dt, linux-serial, devicetree,
	linux-kernel, jirislaby
  Cc: tony.huang, wells.lu, Hammer Hsieh

Hi,

On Wed, 2021-11-10 at 15:51 +0800, Hammer Hsieh wrote:
[...]
> +struct sunplus_uart_port {
> +	char name[16];
> +	struct uart_port uport;
> +	struct sunplus_dma_info *uartdma_rx;
> +	struct sunplus_dma_info *uartdma_tx;
> +	struct clk *clk;
> +	struct reset_control *rstc;
> +	unsigned int pllsys_rate;
> +	struct gpio_desc *rts_gpio;
> +	struct hrtimer rts_check_tx_empty;
> +	struct hrtimer rts_delay_before_send;
> +	struct hrtimer rts_delay_after_send;
> +};
> +struct sunplus_uart_port sunplus_uart_ports[UART_NR];

Does this have to be a global array? I would expect these to be
allocated in the probe function, one at a time.

[...]
> +static int sunplus_uart_probe(struct platform_device *pdev)
> +{
> +	struct resource *res_mem;
> +	struct uart_port *port;
> +	struct clk *clk, *pllsys;
> +	unsigned int pllsys_rate;
> +	int ret, irq;
> +	int idx_offset, idx;
> +	int idx_which_uart;
> +	char peri_name[16];
> +
> +	if (pdev->dev.of_node) {
> +		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
> +		if (pdev->id < 0)
> +			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
> +	}
> +
> +	idx_offset = -1;
> +
> +	if (IS_UARTDMARX_ID(pdev->id))
> +		idx_offset = 0;
> +	else if (IS_UARTDMATX_ID(pdev->id))
> +		idx_offset = UART_DMARX_NR;
> +
> +	/* init txdma or rxdma */
> +	if (idx_offset >= 0) {
> +		clk = devm_clk_get(&pdev->dev, NULL);

Should this be requested by name? Looking at the binding, this could be
UADMA or HWUA?

> +		if (IS_ERR(clk))
> +			return PTR_ERR(clk);
> +
> +		ret = clk_prepare_enable(clk);
> +		if (ret)
> +			return ret;

I suggest to move this down after all required resources are available.
Otherwise you'll have to either disable the clock in the error paths, or
you are left with a running clock if anything below fails.

> +		if (idx_offset == 0)
> +			idx = idx_offset + pdev->id - ID_BASE_DMARX;
> +		else
> +			idx = idx_offset + pdev->id - ID_BASE_DMATX;
> +
> +		res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +		if (!res_mem)
> +			return -ENODEV;
> +
> +		sprintf(peri_name, "PERI%d", (idx & 0x01));
> +
> +		clk = devm_clk_get(&pdev->dev, peri_name);
> +		if (IS_ERR(clk))
> +			return PTR_ERR(clk);
> +
> +		ret = clk_prepare_enable(clk);

Same as above.

> +		if (ret)
> +			return ret;
> +
> +		sunplus_uartdma[idx].addr_phy =
> +			(unsigned long)(res_mem->start);
> +		sunplus_uartdma[idx].membase =
> +			devm_ioremap_resource(&pdev->dev, res_mem);
> +
> +		if (IS_ERR(sunplus_uartdma[idx].membase))
> +			return PTR_ERR(sunplus_uartdma[idx].membase);
> +
> +		if (IS_UARTDMARX_ID(pdev->id)) {
> +			irq = platform_get_irq(pdev, 0);
> +			if (irq < 0)
> +				return -ENODEV;
> +
> +			sunplus_uartdma[idx].irq = irq;
> +		} else {
> +			res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +			if (!res_mem)
> +				return -ENODEV;
> +
> +			sunplus_uartdma[idx].gdma_membase =
> +				devm_ioremap_resource(&pdev->dev, res_mem);
> +
> +			if (IS_ERR(sunplus_uartdma[idx].gdma_membase))
> +				return -EINVAL;
> +		}
> +
> +		if (of_property_read_u32(pdev->dev.of_node, "which-uart", &idx_which_uart) != 0) {
> +			dev_err(&pdev->dev, "\"which-uart\" is not assigned.");
> +			return -EINVAL;
> +		}
> +
> +		if (idx_which_uart >= UART_NR) {
> +			dev_err(&pdev->dev, "\"which-uart\" is not valid.");
> +			return -EINVAL;
> +		}
> +
> +		sunplus_uartdma[idx].which_uart = idx_which_uart;
> +
> +		return 0;
> +	} else if (pdev->id < 0 || pdev->id >= UART_NR)
> +		return -EINVAL;
> +
> +	/* init uart */
> +	port = &sunplus_uart_ports[pdev->id].uport;
> +	if (port->membase)
> +		return -EBUSY;
> +
> +	memset(port, 0, sizeof(*port));
> +
> +	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res_mem)
> +		return -ENODEV;
> +
> +	port->dev = &pdev->dev;
> +	port->mapbase = res_mem->start;
> +
> +	port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
> +	if (IS_ERR(port->membase))
> +		return PTR_ERR(port->membase);
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0)
> +		return -ENODEV;
> +
> +	uart_get_rs485_mode(port);
> +	sunplus_uart_ports[pdev->id].rts_gpio =
> +		devm_gpiod_get(&pdev->dev, "rts", GPIOD_OUT_LOW);
> +	port->rs485_config = sunplus_uart_config_rs485;
> +	sunplus_uart_ports[pdev->id].rts_check_tx_empty.function = NULL;
> +	sunplus_uart_ports[pdev->id].rts_delay_before_send.function = NULL;
> +	sunplus_uart_ports[pdev->id].rts_delay_after_send.function = NULL;
> +	if (port->rs485.flags & SER_RS485_ENABLED)
> +		sunplus_uart_rs485_on(port);
> +
> +	sunplus_uart_ports[pdev->id].clk = devm_clk_get(&pdev->dev, NULL);

Here the same nameless clock as in the loop above is requested again.
Should this be UADMA or HWUA?

> +	if (IS_ERR(sunplus_uart_ports[pdev->id].clk))
> +		return PTR_ERR(sunplus_uart_ports[pdev->id].clk);
> +
> +	ret = clk_prepare_enable(sunplus_uart_ports[pdev->id].clk);
> +	if (ret)
> +		return ret;

Same comment as above. Better to request the reset control before
enabling the clock, for example.

> +
> +	sunplus_uart_ports[pdev->id].rstc =
> +		devm_reset_control_get(&pdev->dev, NULL);

Please use devm_reset_control_get_exclusive() instead.

> +
> +	if (IS_ERR(sunplus_uart_ports[pdev->id].rstc))
> +		return PTR_ERR(sunplus_uart_ports[pdev->id].rstc);
> +
> +	ret = reset_control_deassert(sunplus_uart_ports[pdev->id].rstc);
> +	if (ret)
> +		return ret;
> +
> +	clk = sunplus_uart_ports[pdev->id].clk;
> +	if (IS_ERR(clk))

This can't ever be true, the code above already returned in this case.

[...]
> +static int sunplus_uart_remove(struct platform_device *pdev)
> +{
> +#ifdef CONFIG_PM_RUNTIME_UART
> +	if (pdev->id != 0) {
> +		pm_runtime_disable(&pdev->dev);
> +		pm_runtime_set_suspended(&pdev->dev);
> +	}
> +#endif
> +	uart_remove_one_port(&sunplus_uart_driver,
> +		&sunplus_uart_ports[pdev->id].uport);
> +
> +	if (pdev->id < UART_NR) {
> +		clk_disable_unprepare(sunplus_uart_ports[pdev->id].clk);
> +		reset_control_assert(sunplus_uart_ports[pdev->id].rstc);
> +	}

What about the PERI clocks? This seems to leave them enabled.

regards
Philipp

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC
  2021-11-10  7:51 ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Hammer Hsieh
  2021-11-10  7:51   ` [PATCH v2 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
  2021-11-10  7:51   ` [PATCH v2 2/2] serial:sunplus-uart:Add " Hammer Hsieh
@ 2021-11-10 16:41   ` Andy Shevchenko
  2 siblings, 0 replies; 19+ messages in thread
From: Andy Shevchenko @ 2021-11-10 16:41 UTC (permalink / raw)
  To: Hammer Hsieh
  Cc: Greg Kroah-Hartman, Rob Herring, open list:SERIAL DRIVERS,
	devicetree, Linux Kernel Mailing List, Jiri Slaby, Philipp Zabel,
	tony.huang, wells.lu, Hammer Hsieh

On Wed, Nov 10, 2021 at 9:51 AM Hammer Hsieh <hammerh0314@gmail.com> wrote:
>
> This is a patch series for UART driver for Suplus SP7021 SoC.
>
> Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates
> many peripherals (ex: UART. I2C, SPI, SDIO, eMMC, USB, SD card and
> etc.) into a single chip. It is designed for industrial control.
>
> Refer to:
> https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
> https://tibbo.com/store/plus1.html

...

>  drivers/tty/serial/sunplus-uart.c                  | 1591 ++++++++++++++++++++
>  include/soc/sunplus/sp_uart.h                      |  147 ++

Sorry, but I do not believe this driver requires so many LOCs. Please,
try to get it under 1000, I am pretty sure it's possible and
achievable.

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 19+ messages in thread

* RE: [PATCH v2 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-10  9:50     ` Philipp Zabel
@ 2021-11-11  9:45       ` Hammer Hsieh 謝宏孟
  0 siblings, 0 replies; 19+ messages in thread
From: Hammer Hsieh 謝宏孟 @ 2021-11-11  9:45 UTC (permalink / raw)
  To: Philipp Zabel, Hammer Hsieh, gregkh, robh+dt, linux-serial,
	devicetree, linux-kernel, jirislaby
  Cc: Tony Huang 黃懷厚, Wells Lu 呂芳騰



> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: Wednesday, November 10, 2021 5:50 PM
> To: Hammer Hsieh <hammerh0314@gmail.com>; gregkh@linuxfoundation.org;
> robh+dt@kernel.org; linux-serial@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; jirislaby@kernel.org
> Cc: Tony Huang 黃懷厚 <tony.huang@sunplus.com>; Wells Lu 呂芳騰
> <wells.lu@sunplus.com>; Hammer Hsieh 謝宏孟
> <hammer.hsieh@sunplus.com>
> Subject: Re: [PATCH v2 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
> 
> Hi,
> 
> On Wed, 2021-11-10 at 15:51 +0800, Hammer Hsieh wrote:
> [...]
> > +struct sunplus_uart_port {
> > +	char name[16];
> > +	struct uart_port uport;
> > +	struct sunplus_dma_info *uartdma_rx;
> > +	struct sunplus_dma_info *uartdma_tx;
> > +	struct clk *clk;
> > +	struct reset_control *rstc;
> > +	unsigned int pllsys_rate;
> > +	struct gpio_desc *rts_gpio;
> > +	struct hrtimer rts_check_tx_empty;
> > +	struct hrtimer rts_delay_before_send;
> > +	struct hrtimer rts_delay_after_send; }; struct sunplus_uart_port
> > +sunplus_uart_ports[UART_NR];
> 
> Does this have to be a global array? I would expect these to be allocated in the
> probe function, one at a time.
> 
With console, it uses global array.
  Such as:
  /drivers/tty/serial/ar933x_uart.c
  #ifdef CONFIG_SERIAL_AR933X_CONSOLE
  ar933x_uart_port * ar933x_console_port[ ];
With normal use, it should probe once at a time.
I will think about how to modify it.

> [...]
> > +static int sunplus_uart_probe(struct platform_device *pdev) {
> > +	struct resource *res_mem;
> > +	struct uart_port *port;
> > +	struct clk *clk, *pllsys;
> > +	unsigned int pllsys_rate;
> > +	int ret, irq;
> > +	int idx_offset, idx;
> > +	int idx_which_uart;
> > +	char peri_name[16];
> > +
> > +	if (pdev->dev.of_node) {
> > +		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
> > +		if (pdev->id < 0)
> > +			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
> > +	}
> > +
> > +	idx_offset = -1;
> > +
> > +	if (IS_UARTDMARX_ID(pdev->id))
> > +		idx_offset = 0;
> > +	else if (IS_UARTDMATX_ID(pdev->id))
> > +		idx_offset = UART_DMARX_NR;
> > +
> > +	/* init txdma or rxdma */
> > +	if (idx_offset >= 0) {
> > +		clk = devm_clk_get(&pdev->dev, NULL);
> 
> Should this be requested by name? Looking at the binding, this could be
> UADMA or HWUA?
> 
Yes, it is better requested by name.
But , if request by name , I can't probe both dma_tx and dma_rx with one line.
I will think about how to modify it.

> > +		if (IS_ERR(clk))
> > +			return PTR_ERR(clk);
> > +
> > +		ret = clk_prepare_enable(clk);
> > +		if (ret)
> > +			return ret;
> 
> I suggest to move this down after all required resources are available.
> Otherwise you'll have to either disable the clock in the error paths, or you are
> left with a running clock if anything below fails.
> 
OK, I will modify it.

> > +		if (idx_offset == 0)
> > +			idx = idx_offset + pdev->id - ID_BASE_DMARX;
> > +		else
> > +			idx = idx_offset + pdev->id - ID_BASE_DMATX;
> > +
> > +		res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +		if (!res_mem)
> > +			return -ENODEV;
> > +
> > +		sprintf(peri_name, "PERI%d", (idx & 0x01));
> > +
> > +		clk = devm_clk_get(&pdev->dev, peri_name);
> > +		if (IS_ERR(clk))
> > +			return PTR_ERR(clk);
> > +
> > +		ret = clk_prepare_enable(clk);
> 
> Same as above.
OK, I will modify it.

> 
> > +		if (ret)
> > +			return ret;
> > +
> > +		sunplus_uartdma[idx].addr_phy =
> > +			(unsigned long)(res_mem->start);
> > +		sunplus_uartdma[idx].membase =
> > +			devm_ioremap_resource(&pdev->dev, res_mem);
> > +
> > +		if (IS_ERR(sunplus_uartdma[idx].membase))
> > +			return PTR_ERR(sunplus_uartdma[idx].membase);
> > +
> > +		if (IS_UARTDMARX_ID(pdev->id)) {
> > +			irq = platform_get_irq(pdev, 0);
> > +			if (irq < 0)
> > +				return -ENODEV;
> > +
> > +			sunplus_uartdma[idx].irq = irq;
> > +		} else {
> > +			res_mem = platform_get_resource(pdev, IORESOURCE_MEM,
> 1);
> > +			if (!res_mem)
> > +				return -ENODEV;
> > +
> > +			sunplus_uartdma[idx].gdma_membase =
> > +				devm_ioremap_resource(&pdev->dev, res_mem);
> > +
> > +			if (IS_ERR(sunplus_uartdma[idx].gdma_membase))
> > +				return -EINVAL;
> > +		}
> > +
> > +		if (of_property_read_u32(pdev->dev.of_node, "which-uart",
> &idx_which_uart) != 0) {
> > +			dev_err(&pdev->dev, "\"which-uart\" is not assigned.");
> > +			return -EINVAL;
> > +		}
> > +
> > +		if (idx_which_uart >= UART_NR) {
> > +			dev_err(&pdev->dev, "\"which-uart\" is not valid.");
> > +			return -EINVAL;
> > +		}
> > +
> > +		sunplus_uartdma[idx].which_uart = idx_which_uart;
> > +
> > +		return 0;
> > +	} else if (pdev->id < 0 || pdev->id >= UART_NR)
> > +		return -EINVAL;
> > +
> > +	/* init uart */
> > +	port = &sunplus_uart_ports[pdev->id].uport;
> > +	if (port->membase)
> > +		return -EBUSY;
> > +
> > +	memset(port, 0, sizeof(*port));
> > +
> > +	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (!res_mem)
> > +		return -ENODEV;
> > +
> > +	port->dev = &pdev->dev;
> > +	port->mapbase = res_mem->start;
> > +
> > +	port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
> > +	if (IS_ERR(port->membase))
> > +		return PTR_ERR(port->membase);
> > +
> > +	irq = platform_get_irq(pdev, 0);
> > +	if (irq < 0)
> > +		return -ENODEV;
> > +
> > +	uart_get_rs485_mode(port);
> > +	sunplus_uart_ports[pdev->id].rts_gpio =
> > +		devm_gpiod_get(&pdev->dev, "rts", GPIOD_OUT_LOW);
> > +	port->rs485_config = sunplus_uart_config_rs485;
> > +	sunplus_uart_ports[pdev->id].rts_check_tx_empty.function = NULL;
> > +	sunplus_uart_ports[pdev->id].rts_delay_before_send.function = NULL;
> > +	sunplus_uart_ports[pdev->id].rts_delay_after_send.function = NULL;
> > +	if (port->rs485.flags & SER_RS485_ENABLED)
> > +		sunplus_uart_rs485_on(port);
> > +
> > +	sunplus_uart_ports[pdev->id].clk = devm_clk_get(&pdev->dev, NULL);
> 
> Here the same nameless clock as in the loop above is requested again.
> Should this be UADMA or HWUA?
> 
No, here should be UART clk, each uart didn't use "clock-names" , that's why we use NULL.
In dts UART only use clocks=<&clkc UA0> or <&clkc UA1> or <&clkc UA2>.
We did not use "clock-names".
uart_probe( ) , first init dma , then init uart.

> > +	if (IS_ERR(sunplus_uart_ports[pdev->id].clk))
> > +		return PTR_ERR(sunplus_uart_ports[pdev->id].clk);
> > +
> > +	ret = clk_prepare_enable(sunplus_uart_ports[pdev->id].clk);
> > +	if (ret)
> > +		return ret;
> 
> Same comment as above. Better to request the reset control before enabling
> the clock, for example.
> 
OK, I will modify it.

> > +
> > +	sunplus_uart_ports[pdev->id].rstc =
> > +		devm_reset_control_get(&pdev->dev, NULL);
> 
> Please use devm_reset_control_get_exclusive() instead.
> 
OK, I will modify it.

> > +
> > +	if (IS_ERR(sunplus_uart_ports[pdev->id].rstc))
> > +		return PTR_ERR(sunplus_uart_ports[pdev->id].rstc);
> > +
> > +	ret = reset_control_deassert(sunplus_uart_ports[pdev->id].rstc);
> > +	if (ret)
> > +		return ret;
> > +
> > +	clk = sunplus_uart_ports[pdev->id].clk;
> > +	if (IS_ERR(clk))
> 
> This can't ever be true, the code above already returned in this case.
> 
Indeed, I will modify it.

> [...]
> > +static int sunplus_uart_remove(struct platform_device *pdev) { #ifdef
> > +CONFIG_PM_RUNTIME_UART
> > +	if (pdev->id != 0) {
> > +		pm_runtime_disable(&pdev->dev);
> > +		pm_runtime_set_suspended(&pdev->dev);
> > +	}
> > +#endif
> > +	uart_remove_one_port(&sunplus_uart_driver,
> > +		&sunplus_uart_ports[pdev->id].uport);
> > +
> > +	if (pdev->id < UART_NR) {
> > +		clk_disable_unprepare(sunplus_uart_ports[pdev->id].clk);
> > +		reset_control_assert(sunplus_uart_ports[pdev->id].rstc);
> > +	}
> 
> What about the PERI clocks? This seems to leave them enabled.
> 
In case of dma enable, we should consider it.
I will modify it.


> regards
> Philipp

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-10  7:51   ` [PATCH v2 2/2] serial:sunplus-uart:Add " Hammer Hsieh
  2021-11-10  9:50     ` Philipp Zabel
@ 2021-11-12  8:31     ` kernel test robot
  1 sibling, 0 replies; 19+ messages in thread
From: kernel test robot @ 2021-11-12  8:31 UTC (permalink / raw)
  To: Hammer Hsieh, gregkh, robh+dt, linux-serial, devicetree,
	linux-kernel, jirislaby, p.zabel
  Cc: kbuild-all, tony.huang, wells.lu, Hammer Hsieh

[-- Attachment #1: Type: text/plain, Size: 1826 bytes --]

Hi Hammer,

I love your patch! Yet something to improve:

[auto build test ERROR on tty/tty-testing]
[also build test ERROR on robh/for-next linux/master linus/master v5.15 next-20211112]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Hammer-Hsieh/dt-bindings-serial-Add-bindings-doc-for-Sunplus-SoC-UART-Driver/20211110-165153
base:   https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/bf691d823221e8ab7a6710bcf06c227fcb00ac6d
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Hammer-Hsieh/dt-bindings-serial-Add-bindings-doc-for-Sunplus-SoC-UART-Driver/20211110-165153
        git checkout bf691d823221e8ab7a6710bcf06c227fcb00ac6d
        # save the attached .config to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/tty/serial/sunplus-uart.c:32:10: fatal error: dt-bindings/clock/sp-sp7021.h: No such file or directory
      32 | #include <dt-bindings/clock/sp-sp7021.h>
         |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   compilation terminated.


vim +32 drivers/tty/serial/sunplus-uart.c

  > 32	#include <dt-bindings/clock/sp-sp7021.h>
    33	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66523 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 0/2] Add UART driver for Suplus SP7021 SoC
  2021-11-01  7:48 [PATCH 0/2] Add UART driver for Suplus SP7021 SoC hammer.hsieh
                   ` (2 preceding siblings ...)
  2021-11-10  7:51 ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Hammer Hsieh
@ 2021-11-19  5:19 ` Hammer Hsieh
  2021-11-19  5:19   ` [PATCH v3 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
  2021-11-19  5:19   ` [PATCH v3 2/2] serial:sunplus-uart:Add " Hammer Hsieh
  3 siblings, 2 replies; 19+ messages in thread
From: Hammer Hsieh @ 2021-11-19  5:19 UTC (permalink / raw)
  To: gregkh, robh+dt, linux-serial, devicetree, linux-kernel,
	jirislaby, p.zabel
  Cc: tony.huang, wells.lu, Hammer Hsieh

This is a patch series for UART driver for Suplus SP7021 SoC.

Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates
many peripherals (ex: UART. I2C, SPI, SDIO, eMMC, USB, SD card and
etc.) into a single chip. It is designed for industrial control.

Refer to:
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
https://tibbo.com/store/plus1.html

Hammer Hsieh (2):
  dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  serial:sunplus-uart:Add Sunplus SoC UART Driver

 .../bindings/serial/sunplus,sp7021-uart.yaml       |  58 ++
 MAINTAINERS                                        |   7 +
 drivers/tty/serial/Kconfig                         |  23 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/sunplus-uart.c                  | 903 +++++++++++++++++++++
 include/soc/sunplus/sp_uart.h                      |  93 +++
 6 files changed, 1085 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
 create mode 100644 drivers/tty/serial/sunplus-uart.c
 create mode 100644 include/soc/sunplus/sp_uart.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  2021-11-19  5:19 ` [PATCH v3 " Hammer Hsieh
@ 2021-11-19  5:19   ` Hammer Hsieh
  2021-11-29  0:22     ` Rob Herring
  2021-11-19  5:19   ` [PATCH v3 2/2] serial:sunplus-uart:Add " Hammer Hsieh
  1 sibling, 1 reply; 19+ messages in thread
From: Hammer Hsieh @ 2021-11-19  5:19 UTC (permalink / raw)
  To: gregkh, robh+dt, linux-serial, devicetree, linux-kernel,
	jirislaby, p.zabel
  Cc: tony.huang, wells.lu, Hammer Hsieh

Add bindings doc for Sunplus SoC UART Driver

Signed-off-by: Hammer Hsieh <hammer.hsieh@sunplus.com>
---
Changes in v3:
 - Modify yaml file based on uart driver (remove dma function).

 .../bindings/serial/sunplus,sp7021-uart.yaml       | 58 ++++++++++++++++++++++
 MAINTAINERS                                        |  5 ++
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml

diff --git a/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
new file mode 100644
index 0000000..df11074
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/sunplus,sp7021-uart.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Sunplus SoC SP7021 UART Controller Device Tree Bindings
+
+maintainers:
+  - Tony Huang <tony.huang@sunplus.com>
+  - Hammer Hsieh <hammer.hsieh@sunplus.com>
+  - Wells Lu <wells.lu@sunplus.com>
+
+allOf:
+  - $ref: serial.yaml#
+
+properties:
+  compatible:
+    const: sunplus,sp7021-uart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    aliases {
+            serial0 = &uart0;
+    };
+
+    uart0: serial@9c000900 {
+        compatible = "sunplus,sp7021-uart";
+        reg = <0x9c000900 0x80>;
+        interrupt-parent = <&intc>;
+        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkc 0x28>;
+        resets = <&rstc 0x18>;
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 3b79fd4..f2ee40c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17945,6 +17945,11 @@ L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/ethernet/dlink/sundance.c
 
+SUNPLUS UART DRIVER
+M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
+
 SUPERH
 M:	Yoshinori Sato <ysato@users.sourceforge.jp>
 M:	Rich Felker <dalias@libc.org>
-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-19  5:19 ` [PATCH v3 " Hammer Hsieh
  2021-11-19  5:19   ` [PATCH v3 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
@ 2021-11-19  5:19   ` Hammer Hsieh
  2021-11-19  9:35     ` Andy Shevchenko
  1 sibling, 1 reply; 19+ messages in thread
From: Hammer Hsieh @ 2021-11-19  5:19 UTC (permalink / raw)
  To: gregkh, robh+dt, linux-serial, devicetree, linux-kernel,
	jirislaby, p.zabel
  Cc: tony.huang, wells.lu, Hammer Hsieh

Add Sunplus SoC UART Driver

Signed-off-by: Hammer Hsieh <hammer.hsieh@sunplus.com>
---
Changes in v3:
 - Addressed all comments from Andy Shevchenko and Philipp Zabel.

 MAINTAINERS                       |   2 +
 drivers/tty/serial/Kconfig        |  23 +
 drivers/tty/serial/Makefile       |   1 +
 drivers/tty/serial/sunplus-uart.c | 903 ++++++++++++++++++++++++++++++++++++++
 include/soc/sunplus/sp_uart.h     |  93 ++++
 5 files changed, 1022 insertions(+)
 create mode 100644 drivers/tty/serial/sunplus-uart.c
 create mode 100644 include/soc/sunplus/sp_uart.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f2ee40c..14790a4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17949,6 +17949,8 @@ SUNPLUS UART DRIVER
 M:	Hammer Hsieh <hammer.hsieh@sunplus.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
+F:	drivers/tty/serial/sunplus-uart.c
+F:	include/soc/sunplus/sp-uart.h
 
 SUPERH
 M:	Yoshinori Sato <ysato@users.sourceforge.jp>
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 131a6a5..319f5db 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1561,6 +1561,29 @@ config SERIAL_LITEUART_CONSOLE
 	  and warnings and which allows logins in single user mode).
 	  Otherwise, say 'N'.
 
+config SERIAL_SUNPLUS
+	bool "Sunplus UART support"
+	depends on OF
+	select SERIAL_CORE
+	help
+	  Select this option if you would like to use Sunplus serial port on
+	  Sunplus SoC SP7021.
+	  If you enable this option, Sunplus serial ports in the system will
+	  be registered as ttySx.
+
+config SERIAL_SUNPLUS_CONSOLE
+	bool "Console on Sunplus UART"
+	depends on SERIAL_SUNPLUS
+	select SERIAL_CORE_CONSOLE
+	select SERIAL_EARLYCON
+	help
+	  Select this option if you would like to use a Sunplus UART as the
+	  system console.
+	  Even if you say Y here, the currently visible virtual console
+	  (/dev/tty0) will still be used as the system console by default, but
+	  you can alter that using a kernel command line option such as
+	  "console=ttySx".
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 7da0856..61cc8de 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_SERIAL_RDA)	+= rda-uart.o
 obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
 obj-$(CONFIG_SERIAL_SIFIVE)	+= sifive.o
 obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o
+obj-$(CONFIG_SERIAL_SUNPLUS)	+= sunplus-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)	+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/sunplus-uart.c b/drivers/tty/serial/sunplus-uart.c
new file mode 100644
index 0000000..b339772
--- /dev/null
+++ b/drivers/tty/serial/sunplus-uart.c
@@ -0,0 +1,903 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sunplus SoC UART driver
+ *
+ * Author: Hammer Hsieh <hammer.hsieh@sunplus.com>
+ * Tony Huang <tony.huang@sunplus.com>
+ * Wells Lu <wells.lu@sunplus.com>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/of_platform.h>
+#include <asm/irq.h>
+#include <linux/sysrq.h>
+#include <linux/serial_core.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <soc/sunplus/sp_uart.h>
+
+#define UART_NR			5
+
+static struct uart_driver sunplus_uart_driver;
+
+struct sunplus_uart_port {
+	char name[16];
+	struct uart_port port;
+	struct clk *clk;
+	struct reset_control *rstc;
+};
+
+static inline struct sunplus_uart_port *to_sunplus_uart(struct uart_port *port)
+{
+	return container_of(port, struct sunplus_uart_port, port);
+}
+
+static inline void sp_uart_put_char(struct uart_port *port, unsigned int ch)
+{
+	writel(ch, port->membase + SP_UART_DATA);
+}
+
+static inline u32 sp_uart_line_status_tx_buf_not_full(struct uart_port *port)
+{
+	return ((readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TX)
+		? SP_UART_LSR_TX_NOT_FULL : 0);
+}
+
+static unsigned int sunplus_tx_empty(struct uart_port *port)
+{
+	return ((readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TXE)
+		? TIOCSER_TEMT : 0);
+}
+
+static void sunplus_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	unsigned int mcr = readl(port->membase + SP_UART_MCR);
+
+	if (mctrl & TIOCM_DTR)
+		mcr |= SP_UART_MCR_DTS;
+	else
+		mcr &= ~SP_UART_MCR_DTS;
+
+	if (mctrl & TIOCM_RTS)
+		mcr |= SP_UART_MCR_RTS;
+	else
+		mcr &= ~SP_UART_MCR_RTS;
+
+	if (mctrl & TIOCM_CAR)
+		mcr |= SP_UART_MCR_DCD;
+	else
+		mcr &= ~SP_UART_MCR_DCD;
+
+	if (mctrl & TIOCM_RI)
+		mcr |= SP_UART_MCR_RI;
+	else
+		mcr &= ~SP_UART_MCR_RI;
+
+	if (mctrl & TIOCM_LOOP)
+		mcr |= SP_UART_MCR_LB;
+	else
+		mcr &= ~SP_UART_MCR_LB;
+
+	writel(mcr, port->membase + SP_UART_MCR);
+
+}
+
+static unsigned int sunplus_get_mctrl(struct uart_port *port)
+{
+	unsigned int ret, mcr;
+
+	mcr = readl(port->membase + SP_UART_MCR);
+
+	if (mcr & SP_UART_MCR_DTS)
+		ret |= TIOCM_DTR;
+
+	if (mcr & SP_UART_MCR_RTS)
+		ret |= TIOCM_RTS;
+
+	if (mcr & SP_UART_MCR_DCD)
+		ret |= TIOCM_CAR;
+
+	if (mcr & SP_UART_MCR_RI)
+		ret |= TIOCM_RI;
+
+	if (mcr & SP_UART_MCR_LB)
+		ret |= TIOCM_LOOP;
+
+	if (mcr & SP_UART_MCR_AC)
+		ret |= TIOCM_CTS;
+
+	return ret;
+}
+
+static void sunplus_stop_tx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = readl(port->membase + SP_UART_ISC);
+	isc &= ~SP_UART_ISC_TXM;
+	writel(isc, port->membase + SP_UART_ISC);
+}
+
+static void sunplus_start_tx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = readl(port->membase + SP_UART_ISC);
+	isc |= SP_UART_ISC_TXM;
+	writel(isc, port->membase + SP_UART_ISC);
+}
+
+static void sunplus_stop_rx(struct uart_port *port)
+{
+	unsigned int isc;
+
+	isc = readl(port->membase + SP_UART_ISC);
+	isc &= ~SP_UART_ISC_RXM;
+	writel(isc, port->membase + SP_UART_ISC);
+}
+
+static void sunplus_enable_ms(struct uart_port *port)
+{
+	/* Do nothing */
+}
+
+static void sunplus_break_ctl(struct uart_port *port, int ctl)
+{
+	unsigned long flags;
+	unsigned int lcr;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	lcr = readl(port->membase + SP_UART_LCR);
+
+	if (ctl != 0)
+		lcr |= SP_UART_LCR_BC;	/* start break */
+	else
+		lcr &= ~SP_UART_LCR_BC;	/* stop break */
+
+	writel(lcr, port->membase + SP_UART_LCR);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void transmit_chars(struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->state->xmit;
+
+	if (port->x_char) {
+		sp_uart_put_char(port, port->x_char);
+		port->icount.tx++;
+		port->x_char = 0;
+		return;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+		sunplus_stop_tx(port);
+		return;
+	}
+
+	do {
+		sp_uart_put_char(port, xmit->buf[xmit->tail]);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		port->icount.tx++;
+
+		if (uart_circ_empty(xmit))
+			break;
+	} while (sp_uart_line_status_tx_buf_not_full(port));
+
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (uart_circ_empty(xmit))
+		sunplus_stop_tx(port);
+}
+
+/* called by ISR */
+static void receive_chars(struct uart_port *port)
+{
+	struct tty_struct *tty = port->state->port.tty;
+	unsigned int lsr = readl(port->membase + SP_UART_LSR);
+	unsigned int ch, flag;
+
+	do {
+		ch = readl(port->membase + SP_UART_DATA);
+
+		flag = TTY_NORMAL;
+		port->icount.rx++;
+
+		if (unlikely(lsr & SP_UART_LSR_BRK_ERROR_BITS)) {
+			if (port->cons == NULL)
+				dev_err(port->dev, "UART%d, SP_UART_LSR_BRK_ERROR_BITS, lsr = 0x%08X\n",
+					port->line, lsr);
+
+			if (lsr & SP_UART_LSR_BC) {
+				lsr &= ~(SP_UART_LSR_FE | SP_UART_LSR_PE);
+				port->icount.brk++;
+				if (uart_handle_break(port))
+					goto ignore_char;
+			} else if (lsr & SP_UART_LSR_PE) {
+				if (port->cons == NULL)
+					dev_err(port->dev, "UART%d, SP_UART_LSR_PE\n", port->line);
+				port->icount.parity++;
+			} else if (lsr & SP_UART_LSR_FE) {
+				if (port->cons == NULL)
+					dev_err(port->dev, "UART%d, SP_UART_LSR_FE\n", port->line);
+				port->icount.frame++;
+			}
+			if (lsr & SP_UART_LSR_OE) {
+				if (port->cons == NULL)
+					dev_err(port->dev, "UART%d, SP_UART_LSR_OE\n", port->line);
+				port->icount.overrun++;
+			}
+
+			/*
+			 * Mask off conditions which should be ignored.
+			 */
+
+			/* lsr &= port->read_status_mask; */
+
+			if (lsr & SP_UART_LSR_BC)
+				flag = TTY_BREAK;
+			else if (lsr & SP_UART_LSR_PE)
+				flag = TTY_PARITY;
+			else if (lsr & SP_UART_LSR_FE)
+				flag = TTY_FRAME;
+		}
+
+		if (port->ignore_status_mask & SP_UART_CREAD_DISABLED)
+			goto ignore_char;
+
+		if (uart_handle_sysrq_char(port, ch))
+			goto ignore_char;
+
+		uart_insert_char(port, lsr, SP_UART_LSR_OE, ch, flag);
+
+ignore_char:
+		lsr = readl(port->membase + SP_UART_LSR);
+	} while (lsr & SP_UART_LSR_RX);
+
+	if (tty) {
+		spin_unlock(&port->lock);
+		tty_flip_buffer_push(tty->port);
+		spin_lock(&port->lock);
+	}
+}
+
+static irqreturn_t sunplus_uart_irq(int irq, void *args)
+{
+	struct uart_port *port = (struct uart_port *)args;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	if (readl(port->membase + SP_UART_ISC) & SP_UART_ISC_RX)
+		receive_chars(port);
+
+	if (readl(port->membase + SP_UART_ISC) & SP_UART_ISC_TX)
+		transmit_chars(port);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int sunplus_startup(struct uart_port *port)
+{
+	struct sunplus_uart_port *sup = to_sunplus_uart(port);
+	u32 interrupt_en;
+	int ret;
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (port->line > 0) {
+		ret = pm_runtime_get_sync(port->dev);
+		if (ret < 0)
+			goto out;
+	}
+#endif
+
+	ret = request_irq(port->irq, sunplus_uart_irq, 0, sup->name, port);
+	if (ret)
+		return ret;
+
+	/*
+	 * don't need to use spin_lock_irqsave() because interrupts
+	 * are globally disabled
+	 */
+	spin_lock_irq(&port->lock);
+
+	/* SP_UART_ISC_TXM is enabled in .start_tx() */
+	interrupt_en |= SP_UART_ISC_RXM;
+
+	writel(interrupt_en, port->membase + SP_UART_ISC);
+
+	spin_unlock_irq(&port->lock);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (port->line > 0)
+		pm_runtime_put(port->dev);
+
+	return 0;
+
+out:
+	if (port->line > 0) {
+		pm_runtime_mark_last_busy(port->dev);
+		pm_runtime_put_autosuspend(port->dev);
+	}
+#endif
+	return 0;
+
+}
+
+static void sunplus_shutdown(struct uart_port *port)
+{
+	unsigned int mcr;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	writel(0, port->membase + SP_UART_ISC);
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	free_irq(port->irq, port);
+
+	/* Disable flow control of Tx, so that queued data can be sent out
+	 * There is no way for s/w to let h/w abort in the middle of
+	 * transaction.
+	 * Don't reset module except it's in idle state. Otherwise, it might
+	 * cause bus to hang.
+	 */
+	mcr = readl(port->membase + SP_UART_MCR);
+	mcr &= ~SP_UART_MCR_AC;
+	writel(mcr, port->membase + SP_UART_MCR);
+
+}
+
+static void sunplus_set_termios(struct uart_port *port,
+	struct ktermios *termios, struct ktermios *oldtermios)
+{
+	u32 clk, ext, div, div_l, div_h, baud;
+	u32 lcr, mcr;
+	unsigned long flags;
+
+	clk = port->uartclk;
+
+	baud = uart_get_baud_rate(port, termios, oldtermios, 0, port->uartclk / 16);
+
+	/*
+	 * Send all data in Tx FIFO before changing clock source,
+	 * it should be UART0 only
+	 */
+	while (!(readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TXE))
+		;
+
+	clk += baud >> 1;
+	div = clk / baud;
+	ext = div & 0x0F;
+	div = (div >> 4) - 1;
+	div_l = (div & 0xFF) | (ext << 12);
+	div_h = div >> 8;
+
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		lcr = SP_UART_LCR_WL5;
+		break;
+	case CS6:
+		lcr = SP_UART_LCR_WL6;
+		break;
+	case CS7:
+		lcr = SP_UART_LCR_WL7;
+		break;
+	default:	/* CS8 */
+		lcr = SP_UART_LCR_WL8;
+		break;
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		lcr |= SP_UART_LCR_ST;
+
+	if (termios->c_cflag & PARENB) {
+		lcr |= SP_UART_LCR_PE;
+
+		if (!(termios->c_cflag & PARODD))
+			lcr |= SP_UART_LCR_PR;
+	}
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	port->read_status_mask = 0;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= SP_UART_LSR_PE | SP_UART_LSR_FE;
+
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		port->read_status_mask |= SP_UART_LSR_BC;
+
+	/*
+	 * Characters to ignore
+	 */
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= SP_UART_LSR_FE | SP_UART_LSR_PE;
+
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= SP_UART_LSR_BC;
+
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= SP_UART_LSR_OE;
+	}
+
+	/*
+	 * Ignore all characters if CREAD is not set.
+	 */
+	if ((termios->c_cflag & CREAD) == 0) {
+		port->ignore_status_mask |= SP_UART_CREAD_DISABLED;
+		/* flush rx data FIFO */
+		writel(0, port->membase + SP_UART_RX_RESIDUE);
+	}
+
+	mcr = readl(port->membase + SP_UART_MCR);
+
+	if (termios->c_cflag & CRTSCTS)
+		mcr |= (SP_UART_MCR_AC | SP_UART_MCR_AR);
+	else
+		mcr &= ~(SP_UART_MCR_AC | SP_UART_MCR_AR);
+
+	writel(mcr, port->membase + SP_UART_MCR);
+
+	/* do not set these in emulation */
+	writel(div_h, port->membase + SP_UART_DIV_H);
+	writel(div_l, port->membase + SP_UART_DIV_L);
+	writel(lcr, port->membase + SP_UART_LCR);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void sunplus_set_ldisc(struct uart_port *port,
+				       struct ktermios *termios)
+{
+	int new = termios->c_line;
+
+	if (new == N_PPS) {
+		port->flags |= UPF_HARDPPS_CD;
+		sunplus_enable_ms(port);
+	} else {
+		port->flags &= ~UPF_HARDPPS_CD;
+	}
+}
+
+static const char *sunplus_type(struct uart_port *port)
+{
+	struct sunplus_uart_port *sup = to_sunplus_uart(port);
+
+	return sup->name;
+}
+
+static void sunplus_release_port(struct uart_port *port)
+{
+}
+
+static int sunplus_request_port(struct uart_port *port)
+{
+	return 0;
+}
+
+static void sunplus_config_port(struct uart_port *port, int type)
+{
+	if (type & UART_CONFIG_TYPE) {
+		port->type = PORT_SUNPLUS;
+		sunplus_request_port(port);
+	}
+}
+
+static int sunplus_verify_port(struct uart_port *port, struct serial_struct *serial)
+{
+	return -EINVAL;
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+static int sunplus_poll_init(struct uart_port *port)
+{
+	return 0;
+}
+
+static void sunplus_poll_put_char(struct uart_port *port, unsigned char data)
+{
+	wait_for_xmitr(port);
+	sp_uart_put_char(port, data);
+}
+
+static int sunplus_poll_get_char(struct uart_port *port)
+{
+	unsigned int lsr;
+
+	do {
+		lsr = readl(port->membase + SP_UART_LSR);
+	} while (!(lsr & SP_UART_LSR_RX));
+
+	return readl(port->membase + SP_UART_DATA);
+}
+#endif /* CONFIG_CONSOLE_POLL */
+
+static const struct uart_ops sunplus_uart_ops = {
+	.tx_empty		= sunplus_tx_empty,
+	.set_mctrl		= sunplus_set_mctrl,
+	.get_mctrl		= sunplus_get_mctrl,
+	.stop_tx		= sunplus_stop_tx,
+	.start_tx		= sunplus_start_tx,
+	.stop_rx		= sunplus_stop_rx,
+	.enable_ms		= sunplus_enable_ms,
+	.break_ctl		= sunplus_break_ctl,
+	.startup		= sunplus_startup,
+	.shutdown		= sunplus_shutdown,
+	.set_termios	= sunplus_set_termios,
+	.set_ldisc		= sunplus_set_ldisc,
+	.type			= sunplus_type,
+	.release_port	= sunplus_release_port,
+	.request_port	= sunplus_request_port,
+	.config_port	= sunplus_config_port,
+	.verify_port	= sunplus_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+	.poll_init		= sunplus_poll_init,
+	.poll_put_char	= sunplus_poll_put_char,
+	.poll_get_char	= sunplus_poll_get_char,
+#endif /* CONFIG_CONSOLE_POLL */
+};
+
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+struct sunplus_uart_port *sunplus_console_ports[UART_NR];
+
+static inline void wait_for_xmitr(struct uart_port *port)
+{
+	while (1) {
+		if (sp_uart_line_status_tx_buf_not_full(port))
+			break;
+	}
+}
+
+static void sunplus_uart_console_putchar(struct uart_port *port, int ch)
+{
+	wait_for_xmitr(port);
+	sp_uart_put_char(port, ch);
+}
+
+static void sunplus_uart_console_write(struct console *co,
+	const char *s, unsigned int count)
+{
+	unsigned long flags;
+	int locked = 1;
+
+	local_irq_save(flags);
+
+	if (sunplus_console_ports[co->index]->port.sysrq)
+		locked = 0;
+	else if (oops_in_progress)
+		locked = spin_trylock(&sunplus_console_ports[co->index]->port.lock);
+	else
+		spin_lock(&sunplus_console_ports[co->index]->port.lock);
+
+	uart_console_write(&sunplus_console_ports[co->index]->port,
+		s, count, sunplus_uart_console_putchar);
+
+	if (locked)
+		spin_unlock(&sunplus_console_ports[co->index]->port.lock);
+
+	local_irq_restore(flags);
+}
+
+static int __init sunplus_uart_console_setup(struct console *co, char *options)
+{
+	struct sunplus_uart_port *sup;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	if ((co->index >= UART_NR) || (co->index < 0))
+		return -EINVAL;
+
+	sup = sunplus_console_ports[co->index];
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	return uart_set_options(&sup->port, co, baud, parity, bits, flow);
+}
+
+static struct console sunplus_uart_console = {
+	.name		= "ttyS",
+	.write		= sunplus_uart_console_write,
+	.device		= uart_console_device,
+	.setup		= sunplus_uart_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &sunplus_uart_driver
+};
+#endif
+
+static struct uart_driver sunplus_uart_driver = {
+	.owner		= THIS_MODULE,
+	.driver_name	= "Sunplus_UART",
+	.dev_name	= "ttyS",
+	.major		= TTY_MAJOR,
+	.minor		= 64,
+	.nr			= UART_NR,
+	.cons		= NULL,
+};
+
+static int sunplus_uart_probe(struct platform_device *pdev)
+{
+	struct sunplus_uart_port *sup;
+	struct resource *res_mem;
+	struct uart_port *port;
+	int ret, irq;
+
+	if (pdev->dev.of_node) {
+		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
+		if (pdev->id < 0)
+			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
+	}
+
+	if (pdev->id < 0 || pdev->id >= UART_NR)
+		return -EINVAL;
+
+	sup = devm_kzalloc(&pdev->dev, sizeof(struct sunplus_uart_port),
+			  GFP_KERNEL);
+	if (!sup)
+		return -ENOMEM;
+
+	sup->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(sup->clk)) {
+		dev_err(&pdev->dev, "unable to get UART clock\n");
+		return PTR_ERR(sup->clk);
+	}
+
+	sup->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(sup->rstc))
+		return PTR_ERR(sup->rstc);
+
+	port = &sup->port;
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_mem)
+		return -ENODEV;
+
+	port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
+	if (IS_ERR(port->membase))
+		return PTR_ERR(port->membase);
+
+	ret = clk_prepare_enable(sup->clk);
+	if (ret)
+		return ret;
+
+	port->uartclk = clk_get_rate(sup->clk);
+	if (!port->uartclk) {
+		ret = -EINVAL;
+		goto err_disable_clk;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -ENODEV;
+
+	port->mapbase = res_mem->start;
+	port->line = pdev->id;
+	port->irq = irq;
+	port->dev = &pdev->dev;
+	port->iotype = UPIO_MEM;
+	port->ops = &sunplus_uart_ops;
+	port->flags = UPF_BOOT_AUTOCONF;
+	port->fifosize = 128;
+
+	ret = reset_control_deassert(sup->rstc);
+	if (ret)
+		return ret;
+
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+	if (pdev->id == 0)
+		port->cons = &sunplus_uart_console;
+	sunplus_console_ports[sup->port.line] = sup;
+#endif
+
+	port->private_data = container_of(&sup->port,
+		struct sunplus_uart_port, port);
+
+	sprintf(sup->name, "sp_uart%d", pdev->id);
+
+	ret = uart_add_one_port(&sunplus_uart_driver, &sup->port);
+	if (ret)
+		goto err_disable_clk;
+
+	platform_set_drvdata(pdev, sup);
+
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (pdev->id != 0) {
+		pm_runtime_set_autosuspend_delay(&pdev->dev, 5000);
+		pm_runtime_use_autosuspend(&pdev->dev);
+		pm_runtime_set_active(&pdev->dev);
+		pm_runtime_enable(&pdev->dev);
+	}
+#endif
+	return 0;
+
+err_disable_clk:
+	clk_disable_unprepare(sup->clk);
+	return ret;
+
+}
+
+static int sunplus_uart_remove(struct platform_device *pdev)
+{
+	struct sunplus_uart_port *sup;
+
+	sup = platform_get_drvdata(pdev);
+#ifdef CONFIG_PM_RUNTIME_UART
+	if (pdev->id != 0) {
+		pm_runtime_disable(&pdev->dev);
+		pm_runtime_set_suspended(&pdev->dev);
+	}
+#endif
+	uart_remove_one_port(&sunplus_uart_driver, &sup->port);
+
+	if (pdev->id < UART_NR) {
+		clk_disable_unprepare(sup->clk);
+		reset_control_assert(sup->rstc);
+	}
+
+	return 0;
+}
+
+static int sunplus_uart_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	struct sunplus_uart_port *sup;
+
+	sup = platform_get_drvdata(pdev);
+
+	/* Don't suspend uart0 for cmd line usage */
+	if ((pdev->id < UART_NR) && (pdev->id > 0))
+		reset_control_assert(sup->rstc);
+
+	return 0;
+}
+
+static int sunplus_uart_resume(struct platform_device *pdev)
+{
+	struct sunplus_uart_port *sup;
+
+	sup = platform_get_drvdata(pdev);
+
+	if (pdev->id < UART_NR) {
+		clk_prepare_enable(sup->clk);
+		reset_control_deassert(sup->rstc);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_PM_RUNTIME_UART
+static int sunplus_uart_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct sunplus_uart_port *sup;
+
+	sup = platform_get_drvdata(pdev);
+
+	/* Don't suspend uart0 for cmd line usage */
+	if ((pdev->id < UART_NR) && (pdev->id > 0))
+		reset_control_assert(sup->rstc);
+
+	return 0;
+}
+
+static int sunplus_uart_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct sunplus_uart_port *sup;
+
+	sup = platform_get_drvdata(pdev);
+
+	if (pdev->id < UART_NR) {
+		clk_prepare_enable(sup->clk);
+		reset_control_deassert(sup->rstc);
+	}
+
+	return 0;
+}
+static const struct dev_pm_ops sp7021_uart_pm_ops = {
+	.runtime_suspend = sunplus_uart_runtime_suspend,
+	.runtime_resume  = sunplus_uart_runtime_resume,
+};
+#define sunplus_uart_pm_ops  (&sp7021_uart_pm_ops)
+#endif
+
+static const struct of_device_id sp_uart_of_match[] = {
+	{ .compatible = "sunplus,sp7021-uart" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sp_uart_of_match);
+
+static struct platform_driver sunplus_uart_platform_driver = {
+	.probe		= sunplus_uart_probe,
+	.remove		= sunplus_uart_remove,
+	.suspend	= sunplus_uart_suspend,
+	.resume		= sunplus_uart_resume,
+	.driver = {
+		.name	= "sunplus-uart",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(sp_uart_of_match),
+#ifdef CONFIG_PM_RUNTIME_UART
+		.pm     = sunplus_uart_pm_ops,
+#endif
+	}
+};
+
+static int __init sunplus_uart_init(void)
+{
+	int ret;
+
+#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
+	sunplus_uart_driver.cons = &sunplus_uart_console;
+#endif
+
+	ret = uart_register_driver(&sunplus_uart_driver);
+	if (ret < 0)
+		return ret;
+
+	ret = platform_driver_register(&sunplus_uart_platform_driver);
+	if (ret != 0) {
+		uart_unregister_driver(&sunplus_uart_driver);
+		return ret;
+	}
+
+	return 0;
+}
+module_init(sunplus_uart_init);
+
+#ifdef CONFIG_SERIAL_EARLYCON
+static void sunplus_uart_putc(struct uart_port *port, int c)
+{
+	unsigned int status;
+
+	for (;;) {
+		status = readl(port->membase + SP_UART_LSR);
+		if ((status & SP_UART_LSR_TXE) == SP_UART_LSR_TXE)
+			break;
+		cpu_relax();
+	}
+	writel(c, port->membase + SP_UART_DATA);
+}
+
+static void sunplus_uart_early_write(struct console *con,
+			      const char *s, unsigned int n)
+{
+	struct earlycon_device *dev = con->data;
+
+	uart_console_write(&dev->port, s, n, sunplus_uart_putc);
+}
+
+int __init sunplus_uart_early_setup(struct earlycon_device *device,
+					 const char *opt)
+{
+	if (!(device->port.membase || device->port.iobase))
+		return -ENODEV;
+
+	device->con->write = sunplus_uart_early_write;
+	return 0;
+}
+OF_EARLYCON_DECLARE(sunplus_uart, "sunplus,sp7021-uart", sunplus_uart_early_setup);
+#endif
+
+MODULE_DESCRIPTION("Sunplus UART driver");
+MODULE_AUTHOR("Hammer Hsieh <hammer.hsieh@sunplus.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/soc/sunplus/sp_uart.h b/include/soc/sunplus/sp_uart.h
new file mode 100644
index 0000000..c34c8d0
--- /dev/null
+++ b/include/soc/sunplus/sp_uart.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Sunplus SoC UART driver header file
+ */
+
+#ifndef __SP_UART_H__
+#define __SP_UART_H__
+
+#ifdef CONFIG_DEBUG_SP_UART
+#include <mach/io_map.h>
+
+#define LL_UART_PADDR		PA_IOB_ADDR(18 * 32 * 4)
+#define LL_UART_VADDR		VA_IOB_ADDR(18 * 32 * 4)
+#define LOGI_ADDR_UART0_REG	VA_IOB_ADDR(18 * 32 * 4)
+#endif
+
+/*
+ * UART REG
+ *
+ */
+#define SP_UART_DATA			0x00
+#define SP_UART_LSR				0x04
+#define SP_UART_MSR				0x08
+#define SP_UART_LCR				0x0C
+#define SP_UART_MCR				0x10
+#define SP_UART_DIV_L			0x14
+#define SP_UART_DIV_H			0x18
+#define SP_UART_ISC				0x1C
+#define SP_UART_TX_RESIDUE		0x20
+#define SP_UART_RX_RESIDUE		0x24
+
+/* lsr
+ * 1: trasmit fifo is empty
+ */
+#define SP_UART_LSR_TXE		(1 << 6)
+
+/* interrupt
+ * SP_UART_LSR_BC : break condition
+ * SP_UART_LSR_FE : frame error
+ * SP_UART_LSR_OE : overrun error
+ * SP_UART_LSR_PE : parity error
+ * SP_UART_LSR_RX : 1: receive fifo not empty
+ * SP_UART_LSR_TX : 1: transmit fifo is not full
+ */
+#define SP_UART_CREAD_DISABLED		(1 << 16)
+#define SP_UART_LSR_BC		(1 << 5)
+#define SP_UART_LSR_FE		(1 << 4)
+#define SP_UART_LSR_OE		(1 << 3)
+#define SP_UART_LSR_PE		(1 << 2)
+#define SP_UART_LSR_RX		(1 << 1)
+#define SP_UART_LSR_TX		(1 << 0)
+#define SP_UART_LSR_TX_NOT_FULL		1
+
+#define SP_UART_LSR_BRK_ERROR_BITS	\
+	(SP_UART_LSR_PE | SP_UART_LSR_OE | SP_UART_LSR_FE | SP_UART_LSR_BC)
+
+/* lcr */
+#define SP_UART_LCR_WL5		(0 << 0)
+#define SP_UART_LCR_WL6		(1 << 0)
+#define SP_UART_LCR_WL7		(2 << 0)
+#define SP_UART_LCR_WL8		(3 << 0)
+#define SP_UART_LCR_ST		(1 << 2)
+#define SP_UART_LCR_PE		(1 << 3)
+#define SP_UART_LCR_PR		(1 << 4)
+#define SP_UART_LCR_BC		(1 << 5)
+
+/* isc
+ * SP_UART_ISC_MSM : Modem status ctrl
+ * SP_UART_ISC_LSM : Line status interrupt
+ * SP_UART_ISC_RXM : RX interrupt, when got some input data
+ * SP_UART_ISC_TXM : TX interrupt, when trans start
+ */
+#define SP_UART_ISC_MSM		(1 << 7)
+#define SP_UART_ISC_LSM		(1 << 6)
+#define SP_UART_ISC_RXM		(1 << 5)
+#define SP_UART_ISC_TXM		(1 << 4)
+#define HAS_UART_ISC_FLAGMASK	0x0F
+#define SP_UART_ISC_MS		(1 << 3)
+#define SP_UART_ISC_LS		(1 << 2)
+#define SP_UART_ISC_RX		(1 << 1)
+#define SP_UART_ISC_TX		(1 << 0)
+
+/* modem control register */
+#define SP_UART_MCR_AT		(1 << 7)
+#define SP_UART_MCR_AC		(1 << 6)
+#define SP_UART_MCR_AR		(1 << 5)
+#define SP_UART_MCR_LB		(1 << 4)
+#define SP_UART_MCR_RI		(1 << 3)
+#define SP_UART_MCR_DCD		(1 << 2)
+#define SP_UART_MCR_RTS		(1 << 1)
+#define SP_UART_MCR_DTS		(1 << 0)
+
+#endif /* __SP_UART_H__ */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-19  5:19   ` [PATCH v3 2/2] serial:sunplus-uart:Add " Hammer Hsieh
@ 2021-11-19  9:35     ` Andy Shevchenko
  2021-11-23  3:43       ` Hammer Hsieh 謝宏孟
  0 siblings, 1 reply; 19+ messages in thread
From: Andy Shevchenko @ 2021-11-19  9:35 UTC (permalink / raw)
  To: Hammer Hsieh
  Cc: Greg Kroah-Hartman, Rob Herring, open list:SERIAL DRIVERS,
	devicetree, Linux Kernel Mailing List, Jiri Slaby, Philipp Zabel,
	tony.huang, wells.lu, Hammer Hsieh

On Fri, Nov 19, 2021 at 8:14 AM Hammer Hsieh <hammerh0314@gmail.com> wrote:
>
> Add Sunplus SoC UART Driver

Thanks for update, my comments below.

...

>  drivers/tty/serial/sunplus-uart.c | 903 ++++++++++++++++++++++++++++++++++++++

I believe 50 LOCs easily can be removed (see below for a few examples
I caught just by looking into this for less than 1 minute).

...

>  include/soc/sunplus/sp_uart.h     |  93 ++++

Why do you need this header?

...

> +config SERIAL_SUNPLUS
> +       bool "Sunplus UART support"

No module? Why?

> +       depends on OF

No COMPILE_TEST, why?

> +       select SERIAL_CORE
> +       help
> +         Select this option if you would like to use Sunplus serial port on
> +         Sunplus SoC SP7021.
> +         If you enable this option, Sunplus serial ports in the system will
> +         be registered as ttySx.

If it's ttySx, it most probably 8250 compatible, no?

...

> +/*
> + * Sunplus SoC UART driver
> + *
> + * Author: Hammer Hsieh <hammer.hsieh@sunplus.com>
> + * Tony Huang <tony.huang@sunplus.com>
> + * Wells Lu <wells.lu@sunplus.com>

> + *

Redundant.

> + */

...

> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/console.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/tty.h>
> +#include <linux/tty_flip.h>
> +#include <linux/of_platform.h>
> +#include <asm/irq.h>
> +#include <linux/sysrq.h>
> +#include <linux/serial_core.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/io.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of.h>
> +#include <linux/delay.h>

Sort above alphabetically and get rid of unneeded headers.

> +#include <soc/sunplus/sp_uart.h>

...

> +#define UART_NR                        5

We have this as a config option, why do you need a separate one?

...

> +static struct uart_driver sunplus_uart_driver;

Why global variables?

...
> +struct sunplus_uart_port {
> +       char name[16];

uart_port has a name, what is this one for?

> +       struct uart_port port;

It's better to make it first in the structure to optimize container_of() away.

> +       struct clk *clk;
> +       struct reset_control *rstc;
> +};

...

> +static inline u32 sp_uart_line_status_tx_buf_not_full(struct uart_port *port)
> +{
> +       return ((readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TX)
> +               ? SP_UART_LSR_TX_NOT_FULL : 0);

Use temporary variables for better reading. Here and everywhere else
where it's applicable.

> +}

...

> +       writel(mcr, port->membase + SP_UART_MCR);
> +

Redundant blank line. Check everywhere you have no such waste space.

...

> +static void sunplus_enable_ms(struct uart_port *port)
> +{
> +       /* Do nothing */
> +}

Is this stub needed at all?

...

> +
> +

One blank line is enough.

...

> +                               if (port->cons == NULL)

Don't we have a special API to check if the port is a console or not?

> +                                       dev_err(port->dev, "UART%d, SP_UART_LSR_FE\n", port->line);

...

> +#ifdef CONFIG_PM_RUNTIME_UART
> +       if (port->line > 0) {
> +               ret = pm_runtime_get_sync(port->dev);
> +               if (ret < 0)
> +                       goto out;
> +       }
> +#endif

Can we postpone implementation of it right now, please?
Can you test this [1] series instead?

[1]: https://lore.kernel.org/linux-serial/20211115084203.56478-1-tony@atomide.com/T/#u

...

> +       /* Disable flow control of Tx, so that queued data can be sent out
> +        * There is no way for s/w to let h/w abort in the middle of
> +        * transaction.
> +        * Don't reset module except it's in idle state. Otherwise, it might

the module unless
in an idle

> +        * cause bus to hang.
> +        */

...

> +       /*
> +        * Send all data in Tx FIFO before changing clock source,
> +        * it should be UART0 only
> +        */
> +       while (!(readl(port->membase + SP_UART_LSR) & SP_UART_LSR_TXE))
> +               ;

We do not allow busyloops in the kernel. Consider readl_poll_timeout()
or its atomic variant.

...

> +       clk += baud >> 1;
> +       div = clk / baud;
> +       ext = div & 0x0F;
> +       div = (div >> 4) - 1;
> +       div_l = (div & 0xFF) | (ext << 12);
> +       div_h = div >> 8;

Divisor voodoo should be explained in the comment.

...

> +static void sunplus_release_port(struct uart_port *port)
> +{
> +}
> +
> +static int sunplus_request_port(struct uart_port *port)
> +{
> +       return 0;
> +}

> +static int sunplus_verify_port(struct uart_port *port, struct serial_struct *serial)
> +{
> +       return -EINVAL;
> +}

Why the stubs?

...

> +static inline void wait_for_xmitr(struct uart_port *port)
> +{
> +       while (1) {
> +               if (sp_uart_line_status_tx_buf_not_full(port))
> +                       break;
> +       }

read_poll_timeout() or its atomic variant.

> +}

...

> +       if (pdev->dev.of_node) {

Redundant check

> +               pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
> +               if (pdev->id < 0)
> +                       pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
> +       }

> +

Redundant blank line.

> +       if (pdev->id < 0 || pdev->id >= UART_NR)
> +               return -EINVAL;

...

> +       sup = devm_kzalloc(&pdev->dev, sizeof(struct sunplus_uart_port),
> +                         GFP_KERNEL);

sizeof(*sup) and make it one line.

> +       if (!sup)
> +               return -ENOMEM;

...

> +       sup->clk = devm_clk_get(&pdev->dev, NULL);
> +       if (IS_ERR(sup->clk)) {
> +               dev_err(&pdev->dev, "unable to get UART clock\n");
> +               return PTR_ERR(sup->clk);

Respect deferred probe by

return dev_err_probe(...);

> +       }

...

> +       res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

> +       if (!res_mem)
> +               return -ENODEV;
> +

Redundant check, besides that...

> +       port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
> +       if (IS_ERR(port->membase))
> +               return PTR_ERR(port->membase);

...there is an API that does these two in one.

...

> +       port->uartclk = clk_get_rate(sup->clk);
> +       if (!port->uartclk) {
> +               ret = -EINVAL;

> +               goto err_disable_clk;

Instead use devm_add_action_or_reset() as many other drivers do in the kernel.

> +       }

...

> +       irq = platform_get_irq(pdev, 0);
> +       if (irq < 0)
> +               return -ENODEV;

What's wrong with the error code in the irq variable?

...

> +       port->private_data = container_of(&sup->port,
> +               struct sunplus_uart_port, port);

What does this mean?

...

> +static const struct of_device_id sp_uart_of_match[] = {
> +       { .compatible = "sunplus,sp7021-uart" },

> +       {},

No comma for terminator entries.

> +};

...

> +static struct platform_driver sunplus_uart_platform_driver = {
> +       .probe          = sunplus_uart_probe,
> +       .remove         = sunplus_uart_remove,
> +       .suspend        = sunplus_uart_suspend,
> +       .resume         = sunplus_uart_resume,
> +       .driver = {
> +               .name   = "sunplus-uart",

> +               .owner  = THIS_MODULE,

This is done by registration call, no?

> +               .of_match_table = of_match_ptr(sp_uart_of_match),

Effectively a warning (but you don't see it since COMPILE_TEST is missed).
Hint: drop of_match_ptr() completely.

> +#ifdef CONFIG_PM_RUNTIME_UART
> +               .pm     = sunplus_uart_pm_ops,
> +#endif
> +       }
> +};

...

> +       ret = platform_driver_register(&sunplus_uart_platform_driver);

> +       if (ret != 0) {

Keep the same style over the driver.

> +               uart_unregister_driver(&sunplus_uart_driver);
> +               return ret;
> +       }

...

> +       for (;;) {
> +               status = readl(port->membase + SP_UART_LSR);
> +               if ((status & SP_UART_LSR_TXE) == SP_UART_LSR_TXE)
> +                       break;
> +               cpu_relax();
> +       }

real_poll_timeout*()

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 19+ messages in thread

* RE: [PATCH v3 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
  2021-11-19  9:35     ` Andy Shevchenko
@ 2021-11-23  3:43       ` Hammer Hsieh 謝宏孟
  0 siblings, 0 replies; 19+ messages in thread
From: Hammer Hsieh 謝宏孟 @ 2021-11-23  3:43 UTC (permalink / raw)
  To: Andy Shevchenko, Hammer Hsieh
  Cc: Greg Kroah-Hartman, Rob Herring, open list:SERIAL DRIVERS,
	devicetree, Linux Kernel Mailing List, Jiri Slaby, Philipp Zabel,
	Tony Huang 黃懷厚,
	Wells Lu 呂芳騰

Hi, Andy Shevchenko :

I may not fully understand all your comments.
But most of them I will modify when next submit.
I try to answer all your comments below.
And also have some question about some of your comments.

Thanks
Regards,
Hammer

> -----Original Message-----
> From: Andy Shevchenko <andy.shevchenko@gmail.com>
> Sent: Friday, November 19, 2021 5:35 PM
> To: Hammer Hsieh <hammerh0314@gmail.com>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Rob Herring
> <robh+dt@kernel.org>; open list:SERIAL DRIVERS
> <linux-serial@vger.kernel.org>; devicetree <devicetree@vger.kernel.org>;
> Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; Jiri Slaby
> <jirislaby@kernel.org>; Philipp Zabel <p.zabel@pengutronix.de>; Tony Huang
> 黃懷厚 <tony.huang@sunplus.com>; Wells Lu 呂芳騰
> <wells.lu@sunplus.com>; Hammer Hsieh 謝宏孟
> <hammer.hsieh@sunplus.com>
> Subject: Re: [PATCH v3 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
> 
> On Fri, Nov 19, 2021 at 8:14 AM Hammer Hsieh <hammerh0314@gmail.com>
> wrote:
> >
> > Add Sunplus SoC UART Driver
> 
> Thanks for update, my comments below.
> 
> ...
> 
> >  drivers/tty/serial/sunplus-uart.c | 903
> > ++++++++++++++++++++++++++++++++++++++
> 
> I believe 50 LOCs easily can be removed (see below for a few examples I caught
> just by looking into this for less than 1 minute).
> 
> ...
> 
> >  include/soc/sunplus/sp_uart.h     |  93 ++++
> 
> Why do you need this header?
> 
Ok, will remove header file, reg define will move to sunplus-uart.c

> ...
> 
> > +config SERIAL_SUNPLUS
> > +       bool "Sunplus UART support"
> 
> No module? Why?

Will add tristate for it. I will confirm load/unload *.ko for it.

> 
> > +       depends on OF
> 
> No COMPILE_TEST, why?

Will add COMPILE_TEST for it.

> 
> > +       select SERIAL_CORE
> > +       help
> > +         Select this option if you would like to use Sunplus serial port on
> > +         Sunplus SoC SP7021.
> > +         If you enable this option, Sunplus serial ports in the system will
> > +         be registered as ttySx.
> 
> If it's ttySx, it most probably 8250 compatible, no?
> 

No , it is a single chip, not 8250 compatible.
I plan to use 'ttySUP' for Sunplus SoC UART.
We define PORT_SUNPLUS 123 at /include/uapi/linux/serial_core.h
Is that ok?

> ...
> 
> > +/*
> > + * Sunplus SoC UART driver
> > + *
> > + * Author: Hammer Hsieh <hammer.hsieh@sunplus.com>
> > + * Tony Huang <tony.huang@sunplus.com>
> > + * Wells Lu <wells.lu@sunplus.com>
> 
> > + *
> 
> Redundant.
> 

Ok , will remove it.

> > + */
> 
> ...
> 
> > +#include <linux/module.h>
> > +#include <linux/init.h>
> > +#include <linux/console.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/tty.h>
> > +#include <linux/tty_flip.h>
> > +#include <linux/of_platform.h>
> > +#include <asm/irq.h>
> > +#include <linux/sysrq.h>
> > +#include <linux/serial_core.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/io.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/of.h>
> > +#include <linux/delay.h>
> 
> Sort above alphabetically and get rid of unneeded headers.
> 
> > +#include <soc/sunplus/sp_uart.h>
> 

Ok , will do it.

> ...
> 
> > +#define UART_NR                        5
> 
> We have this as a config option, why do you need a separate one?
> 

Can I keep UART_NR in sunplus-uart.c ?
If all uart driver define CONFIG_xxx_UART_NR in Kconfig.
Kconfig will get big very fast.
In sunplus-uart.c just only one line code.
In Kconfig takes 8 ~ 10 line code.

> ...
> 
> > +static struct uart_driver sunplus_uart_driver;
> 
> Why global variables?
> 

It is define for struct console { }
I will move it to close to struct console { }

> ...
> > +struct sunplus_uart_port {
> > +       char name[16];
> 
> uart_port has a name, what is this one for?
> 

Ok , will remove it.

> > +       struct uart_port port;
> 
> It's better to make it first in the structure to optimize container_of() away.
> 
> > +       struct clk *clk;
> > +       struct reset_control *rstc;
> > +};
> 

Ok, thanks for the information.

> ...
> 
> > +static inline u32 sp_uart_line_status_tx_buf_not_full(struct
> > +uart_port *port) {
> > +       return ((readl(port->membase + SP_UART_LSR) &
> SP_UART_LSR_TX)
> > +               ? SP_UART_LSR_TX_NOT_FULL : 0);
> 
> Use temporary variables for better reading. Here and everywhere else where
> it's applicable.
> 
> > +}
> 

Ok, will modify it.

> ...
> 
> > +       writel(mcr, port->membase + SP_UART_MCR);
> > +
> 
> Redundant blank line. Check everywhere you have no such waste space.
> 

Ok, will remove it.

> ...
> 
> > +static void sunplus_enable_ms(struct uart_port *port) {
> > +       /* Do nothing */
> > +}
> 
> Is this stub needed at all?
> 

No, will remove it.

> ...
> 
> > +
> > +
> 
> One blank line is enough.
> 

Ok, will remove it.

> ...
> 
> > +                               if (port->cons == NULL)
> 
> Don't we have a special API to check if the port is a console or not?
> 

Can you show me the API ?

> > +                                       dev_err(port->dev,
> "UART%d,
> > + SP_UART_LSR_FE\n", port->line);
> 
> ...
> 
> > +#ifdef CONFIG_PM_RUNTIME_UART
> > +       if (port->line > 0) {
> > +               ret = pm_runtime_get_sync(port->dev);
> > +               if (ret < 0)
> > +                       goto out;
> > +       }
> > +#endif
> 
> Can we postpone implementation of it right now, please?
> Can you test this [1] series instead?
> 
> [1]:
> https://lore.kernel.org/linux-serial/20211115084203.56478-1-tony@atomide.c
> om/T/#u
> 

I don't understand what's going on this issue?

> ...
> 
> > +       /* Disable flow control of Tx, so that queued data can be sent out
> > +        * There is no way for s/w to let h/w abort in the middle of
> > +        * transaction.
> > +        * Don't reset module except it's in idle state. Otherwise, it
> > + might
> 
> the module unless
> in an idle
> 
> > +        * cause bus to hang.
> > +        */
> 
> ...
> 
> > +       /*
> > +        * Send all data in Tx FIFO before changing clock source,
> > +        * it should be UART0 only
> > +        */
> > +       while (!(readl(port->membase + SP_UART_LSR) &
> SP_UART_LSR_TXE))
> > +               ;
> 
> We do not allow busyloops in the kernel. Consider readl_poll_timeout() or its
> atomic variant.
> 

Ok, will modify for it.

> ...
> 
> > +       clk += baud >> 1;
> > +       div = clk / baud;
> > +       ext = div & 0x0F;
> > +       div = (div >> 4) - 1;
> > +       div_l = (div & 0xFF) | (ext << 12);
> > +       div_h = div >> 8;
> 
> Divisor voodoo should be explained in the comment.
> 

Ok, will add explanation for it.

> ...
> 
> > +static void sunplus_release_port(struct uart_port *port) { }
> > +
> > +static int sunplus_request_port(struct uart_port *port) {
> > +       return 0;
> > +}
> 
> > +static int sunplus_verify_port(struct uart_port *port, struct
> > +serial_struct *serial) {
> > +       return -EINVAL;
> > +}
> 
> Why the stubs?
> 

Will modify it.
Like below:
  if((type!= PORT_UNKNOWN) && (type != PORT_SUNPLUS))
    return -EINVAL;
  return 0;

> ...
> 
> > +static inline void wait_for_xmitr(struct uart_port *port) {
> > +       while (1) {
> > +               if (sp_uart_line_status_tx_buf_not_full(port))
> > +                       break;
> > +       }
> 
> read_poll_timeout() or its atomic variant.
> 

Ok, will modify it.

> > +}
> 
> ...
> 
> > +       if (pdev->dev.of_node) {
> 
> Redundant check

Sure, will remove it.

> 
> > +               pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
> > +               if (pdev->id < 0)
> > +                       pdev->id = of_alias_get_id(pdev->dev.of_node,
> "uart");
> > +       }
> 
> > +
> 
> Redundant blank line.

Ok, will remove it.

> 
> > +       if (pdev->id < 0 || pdev->id >= UART_NR)
> > +               return -EINVAL;
> 
> ...
> 
> > +       sup = devm_kzalloc(&pdev->dev, sizeof(struct sunplus_uart_port),
> > +                         GFP_KERNEL);
> 
> sizeof(*sup) and make it one line.
> 

Ok, will modify it.

> > +       if (!sup)
> > +               return -ENOMEM;
> 
> ...
> 
> > +       sup->clk = devm_clk_get(&pdev->dev, NULL);
> > +       if (IS_ERR(sup->clk)) {
> > +               dev_err(&pdev->dev, "unable to get UART clock\n");
> > +               return PTR_ERR(sup->clk);
> 
> Respect deferred probe by
> 
> return dev_err_probe(...);
> 

Ok, will modify it.

> > +       }
> 
> ...
> 
> > +       res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> 
> > +       if (!res_mem)
> > +               return -ENODEV;
> > +
> 
> Redundant check, besides that...

Ok, will remove it.

> 
> > +       port->membase = devm_ioremap_resource(&pdev->dev,
> res_mem);
> > +       if (IS_ERR(port->membase))
> > +               return PTR_ERR(port->membase);
> 
> ...there is an API that does these two in one.
> 

API of_ioremap(res, offset, sizeof(xx), "xxx") can do it.
But we didn't use reg-names for it in dts.
I think it is better keep orginal platform_get_resource() + devm_ioremap_resource().

> ...
> 
> > +       port->uartclk = clk_get_rate(sup->clk);
> > +       if (!port->uartclk) {
> > +               ret = -EINVAL;
> 
> > +               goto err_disable_clk;
> 
> Instead use devm_add_action_or_reset() as many other drivers do in the
> kernel.
> 
> > +       }
> 

Ok, will modify it.

> ...
> 
> > +       irq = platform_get_irq(pdev, 0);
> > +       if (irq < 0)
> > +               return -ENODEV;
> 
> What's wrong with the error code in the irq variable?
> 

Will change 'return -ENODEV' to 'return irq'.

> ...
> 
> > +       port->private_data = container_of(&sup->port,
> > +               struct sunplus_uart_port, port);
> 
> What does this mean?
> 

Previous code use it to store 'struct sunplus_uart_port' pointer, will remove it.

> ...
> 
> > +static const struct of_device_id sp_uart_of_match[] = {
> > +       { .compatible = "sunplus,sp7021-uart" },
> 
> > +       {},
> 
> No comma for terminator entries.
> 

Ok, will remove it.

> > +};
> 
> ...
> 
> > +static struct platform_driver sunplus_uart_platform_driver = {
> > +       .probe          = sunplus_uart_probe,
> > +       .remove         = sunplus_uart_remove,
> > +       .suspend        = sunplus_uart_suspend,
> > +       .resume         = sunplus_uart_resume,
> > +       .driver = {
> > +               .name   = "sunplus-uart",
> 
> > +               .owner  = THIS_MODULE,
> 
> This is done by registration call, no?
> 

Ok, will remove it.

> > +               .of_match_table = of_match_ptr(sp_uart_of_match),
> 
> Effectively a warning (but you don't see it since COMPILE_TEST is missed).
> Hint: drop of_match_ptr() completely.
> 

Ok, thanks for the information. I will add COMPILE_TEST in Kconfig.

> > +#ifdef CONFIG_PM_RUNTIME_UART
> > +               .pm     = sunplus_uart_pm_ops,
> > +#endif
> > +       }
> > +};
> 
> ...
> 
> > +       ret = platform_driver_register(&sunplus_uart_platform_driver);
> 
> > +       if (ret != 0) {
> 
> Keep the same style over the driver.
> 

Ok, will modify it.

> > +               uart_unregister_driver(&sunplus_uart_driver);
> > +               return ret;
> > +       }
> 
> ...
> 
> > +       for (;;) {
> > +               status = readl(port->membase + SP_UART_LSR);
> > +               if ((status & SP_UART_LSR_TXE) == SP_UART_LSR_TXE)
> > +                       break;
> > +               cpu_relax();
> > +       }
> 
> real_poll_timeout*()
> 

Ok, will modify it.

> --
> With Best Regards,
> Andy Shevchenko

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
  2021-11-19  5:19   ` [PATCH v3 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
@ 2021-11-29  0:22     ` Rob Herring
  0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring @ 2021-11-29  0:22 UTC (permalink / raw)
  To: Hammer Hsieh
  Cc: Hammer Hsieh, p.zabel, linux-kernel, devicetree, wells.lu,
	robh+dt, tony.huang, linux-serial, jirislaby, gregkh

On Fri, 19 Nov 2021 13:19:22 +0800, Hammer Hsieh wrote:
> Add bindings doc for Sunplus SoC UART Driver
> 
> Signed-off-by: Hammer Hsieh <hammer.hsieh@sunplus.com>
> ---
> Changes in v3:
>  - Modify yaml file based on uart driver (remove dma function).
> 
>  .../bindings/serial/sunplus,sp7021-uart.yaml       | 58 ++++++++++++++++++++++
>  MAINTAINERS                                        |  5 ++
>  2 files changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2021-11-29  0:24 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-01  7:48 [PATCH 0/2] Add UART driver for Suplus SP7021 SoC hammer.hsieh
2021-11-01  7:48 ` [PATCH 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver hammer.hsieh
2021-11-01 13:20   ` Rob Herring
2021-11-01 19:34   ` Rob Herring
2021-11-01  7:48 ` [PATCH 2/2] serial:sunplus-uart:Add " hammer.hsieh
2021-11-01  7:56   ` Greg KH
2021-11-10  7:51 ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Hammer Hsieh
2021-11-10  7:51   ` [PATCH v2 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
2021-11-10  7:51   ` [PATCH v2 2/2] serial:sunplus-uart:Add " Hammer Hsieh
2021-11-10  9:50     ` Philipp Zabel
2021-11-11  9:45       ` Hammer Hsieh 謝宏孟
2021-11-12  8:31     ` kernel test robot
2021-11-10 16:41   ` [PATCH v2 0/2] Add UART driver for Suplus SP7021 SoC Andy Shevchenko
2021-11-19  5:19 ` [PATCH v3 " Hammer Hsieh
2021-11-19  5:19   ` [PATCH v3 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
2021-11-29  0:22     ` Rob Herring
2021-11-19  5:19   ` [PATCH v3 2/2] serial:sunplus-uart:Add " Hammer Hsieh
2021-11-19  9:35     ` Andy Shevchenko
2021-11-23  3:43       ` Hammer Hsieh 謝宏孟

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