From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFF77C433EF for ; Tue, 7 Sep 2021 06:55:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90AB7610FF for ; Tue, 7 Sep 2021 06:55:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235544AbhIGG4n (ORCPT ); Tue, 7 Sep 2021 02:56:43 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:58136 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235276AbhIGG4l (ORCPT ); Tue, 7 Sep 2021 02:56:41 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 1872qDNW030676; Tue, 7 Sep 2021 08:55:18 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=pPWWaNwMDzyikRTWDISy5sjjTX8UIPo1qSx4LUPLwxA=; b=mxD6e0fuEA913caHEUABA1NDOa6dqb+EnzE8ByiidNC5kiF0ZcpYnou85R0Y8H1sJbuU oionhz6yi3OMoprhgzrtNW6hzviBPJAhw5UmwUTH7BVNaE+Gh+7OyeKq1Iu4glQf84bI Y58qydwyqegXSDY4mG1O4yeZjzR3sDFzz5AU2eqXjROo3AGkmHNAPChNemk2MNF8+20V 8K1aY+kdrWdwZqHhOhdAm5pyyn7Cx35LcCyDQbArSr99BMzXfFdYbTei0icrtVc6lUJT aG4mMzeXWvIwfyvm6/yChPkPHjJyLtwQRlftfyHRMTW3yfzbt3yqZYxMJdpI2ucKboWK Hg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 3awyp0rwwa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Sep 2021 08:55:18 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 97DC910002A; Tue, 7 Sep 2021 08:55:15 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag1node3.st.com [10.75.127.3]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 64CE52122E8; Tue, 7 Sep 2021 08:55:15 +0200 (CEST) Received: from lmecxl0951.lme.st.com (10.75.127.45) by SFHDAG1NODE3.st.com (10.75.127.3) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 7 Sep 2021 08:55:14 +0200 Subject: Re: [PATCH] drm/stm: ltdc: add layer alpha support To: Raphael GALLAIS-POU - foss , "Philippe CORNU - foss" , Benjamin Gaignard CC: David Airlie , Daniel Vetter , "Maxime Coquelin" , Alexandre TORGUE - foss , "dri-devel@lists.freedesktop.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Raphael GALLAIS-POU References: <20210903085740.23108-1-raphael.gallais-pou@foss.st.com> From: yannick Fertre Message-ID: <19331273-3464-869e-8e62-a0c3e096ed70@foss.st.com> Date: Tue, 7 Sep 2021 08:55:14 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210903085740.23108-1-raphael.gallais-pou@foss.st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG1NODE3.st.com (10.75.127.3) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-07_02,2021-09-03_01,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Raphael, thanks for the patch. Acked-by: Yannick Fertre Reviewed-by: Yannick Fertre On 9/3/21 10:58 AM, Raphael GALLAIS-POU - foss wrote: > Android Hardware Composer supports alpha values applied to layers. > Enabling non-opaque layers for the STM CRTC could help offload GPU > resources for screen composition. > > Signed-off-by: Raphael Gallais-Pou > --- > drivers/gpu/drm/stm/ltdc.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c > index 195de30eb90c..e0fef8bacfa8 100644 > --- a/drivers/gpu/drm/stm/ltdc.c > +++ b/drivers/gpu/drm/stm/ltdc.c > @@ -845,7 +845,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, > LXCFBLR_CFBLL | LXCFBLR_CFBP, val); > > /* Specifies the constant alpha value */ > - val = CONSTA_MAX; > + val = newstate->alpha >> 8; > reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); > > /* Specifies the blending factors */ > @@ -997,6 +997,8 @@ static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, > > drm_plane_helper_add(plane, <dc_plane_helper_funcs); > > + drm_plane_create_alpha_property(plane); > + > DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); > > return plane; >