Re: [PATCH v4 4/4] ARM: dts: aspeed: Add eSPI node

[Andrei Kartashev <a.kartashev@yadro.com>]

Hi Chia-Wei,

How is it about g5? Why did you add definition only for g6 here?


On Wed, 2021-09-01 at 11:30 +0800, Chia-Wei Wang wrote:
> Add eSPI to the device tree for Aspeed 5/6th generation SoCs.
> 
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi
> b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f96607b7b4e2..47dc0b3993d1 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -364,6 +364,23 @@
>                                 status = "disabled";
>                         };
>  
> +                       espi: espi@1e6ee000 {
> +                               compatible = "aspeed,ast2600-espi",
> "simple-mfd", "syscon";
> +                               reg = <0x1e6ee000 0x1000>;
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <1>;
> +                               ranges = <0x0 0x1e6ee000 0x1000>;
> +
> +                               espi_ctrl: espi-ctrl@0 {
> +                                       compatible = "aspeed,ast2600-
> espi-ctrl";
> +                                       reg = <0x0 0x800>;
> +                                       interrupts = <GIC_SPI 42
> IRQ_TYPE_LEVEL_HIGH>;
> +                                       clocks = <&syscon
> ASPEED_CLK_GATE_ESPICLK>;
> +                                       status = "disabled";
> +                               };
> +                       };
> +
>                         gpio0: gpio@1e780000 {
>                                 #gpio-cells = <2>;
>                                 gpio-controller;

-- 
Best regards,
Andrei Kartashev