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From: Michal Simek <michal.simek@xilinx.com>
To: Mark Brown <broonie@kernel.org>, Michal Simek <michal.simek@xilinx.com>
Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
	linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] spi: xilinx: Use standard num-cs binding
Date: Mon, 30 Mar 2015 08:46:10 +0200	[thread overview]
Message-ID: <1bd88fda-314c-496a-ba8b-e9292f9c411b@BY2FFO11FD023.protection.gbl> (raw)
In-Reply-To: <20150327175318.GG1743@sirena.org.uk>

Hi Mark,

On 03/27/2015 06:53 PM, Mark Brown wrote:
> On Fri, Mar 27, 2015 at 11:55:49AM +0100, Michal Simek wrote:
> 
> Please fix your mail client to word wrap within paragraphs at less than
> 80 columns - this makes your mails easier to read and reply to.

You are the first one who had problem with this. But I have setup lower
limit and hopefully it is better now.


>> On 03/08/2015 08:00 PM, Mark Brown wrote:
>>> On Fri, Jan 16, 2015 at 01:55:14PM +0100, Michal Simek wrote:
>>>> Use standard num-cs binding property and setup
>>>> "xlnx,num-ss-bits" as deprecated.
> 
>>> Why?  These properties mean different things - num-cs is a bit confused
>>> and is the total number of available chip selects for the system (which
>>> could include GPIOs) while num-ss-bits is the size of the bitfield
>>> (which could include things not actually mapped out properly/successfully 
>>> or something if the hardware designers were feeling particularly inspired).
> 
>> I was checking meaning of num-ss-bits and meaning is Number of slaves (taking
>> explanation from Vivado 2014.4) Range 1-32.
>> http://www.xilinx.com/support/documentation/ip_documentation/axi_spi/v1_02_a/axi_spi_ds742.pdf
>> Table 1 - page 4
> 
>> Checking through the hw design every pin is connected to device to do chip select.
>> That's why I think that num-cs (based on spi-bus.txt) is the right property.
> 
> Remember that we can at least in theory have additional chip selects
> that aren't controlled by the IP block but are instead GPIOs.  

I agree with you but this can be generic case for every SPI driver. Also
using external decoder is possible for every driver. Maybe there are
others options via I2C too.

> There's
> also some potential confusion for users between the number of chip
> selects in use in a given system and the size of the bitfield that the
> driver needs to take care of.

num-ss-bits is autogenerated directly from design tools for particular
hardware design and this size is exactly setup and hardcoded. (num-cs
can be just the same case)
If there are 5 bits there are 5 wires from IP. And value of num-ss-bits
and num-cs will be the same.

If user wants to use less lines then physically available we could
potentially extend binding to say. num-ss-bit - number of chip selects
available in hardware. num-cs - number of chip selects used by the driver.
But I expect that this will be rejected because it is software setting
not hardware description.

It is not a problem to still use num-ss-bits in the driver binding
but I still think that "standard" num-cs binding can be also used,
because values will be the same all the time.

For all that cases with GPIO, I2C, etc binding needs to be extended
and to be honest setting up CS with GPIO is easy to do in FPGA and
test it.

Thanks,
Michal

  reply	other threads:[~2015-03-30  6:46 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-16 12:55 Michal Simek
2015-02-12  9:45 ` Michal Simek
     [not found] ` <CAHTX3dJRGhwo7FW+VJxfEJmx-9FdjFN5EnxG0RRDfMOm3=VU4A@mail.gmail.com>
2015-02-14  5:35   ` Mark Brown
2015-02-23 10:22     ` Michal Simek
2015-02-24 14:52       ` Mark Brown
2015-03-08 19:00 ` Mark Brown
2015-03-27 10:55   ` Michal Simek
2015-03-27 17:53     ` Mark Brown
2015-03-30  6:46       ` Michal Simek [this message]
2015-03-31  5:47         ` Mark Brown
2015-03-31  8:16           ` Michal Simek
2015-03-31 11:16             ` Mark Brown
2015-03-31 11:25               ` Michal Simek
2015-03-31 12:24                 ` Mark Brown

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