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From: "Shai Fultheim" <shai@ftcon.com>
To: "'Jeff Garzik'" <jgarzik@pobox.com>
Cc: "'Bartlomiej Zolnierkiewicz'" <B.Zolnierkiewicz@elka.pw.edu.pl>,
	"'Andrew Morton'" <akpm@osdl.org>,
	"'Linux Kernel Mailing List'" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH] Multiple (ICH3) IDE-controllers in a system
Date: Sat, 15 May 2004 21:20:06 -0700	[thread overview]
Message-ID: <200405160420.BMB67029@ms6.netsolmail.com> (raw)
In-Reply-To: <40A66819.9040806@pobox.com>

Jeff,

Here is what I see: pci_scan_single_device() at
http://lxr.linux.no/source/drivers/pci/probe.c?v=2.6.5#L590 which calls to
pci_fixup_device() (line 601) which in turn use the quirks table at
http://lxr.linux.no/source/arch/i386/pci/fixup.c?v=2.6.5#L190 (my chipset is
in line 248).  The quirks table for ICH3 use pci_fixup_ide_trash()at
http://lxr.linux.no/source/arch/i386/pci/fixup.c?v=2.6.5#L90 - this reset
the BARs for the device.  Resetting the all (4) BARs of (ICH3) IDE
controllers will cause them to use the defaults BARs (0x170, 0x1f0) in
ide_hwif_configure() at
http://lxr.linux.no/source/drivers/ide/setup-pci.c?v=2.6.5#L420.  This will
fail with any subsequent (ICH3) IDE controllers (two devices can't use the
same ports).  

Agree or not?

My patch (not sure there is nicer way to handle this), will not allow reset
of BARs if you hit any ICH3 which is not the first one. This will rely on
BIOS setting for all other controllers.

--Shai


-----Original Message-----
From: Jeff Garzik [mailto:jgarzik@pobox.com] 
Sent: Saturday, May 15, 2004 11:57
To: Linux Kernel Mailing List
Cc: shai@ftcon.com; Bartlomiej Zolnierkiewicz; Andrew Morton
Subject: Re: [PATCH] Multiple (ICH3) IDE-controllers in a system

Linux Kernel Mailing List wrote:
> ChangeSet 1.1627, 2004/05/15 09:42:40-07:00, shai@ftcon.com
> 
> 	[PATCH] Multiple (ICH3) IDE-controllers in a system
> 	
> 	This fixes a problem with multiple IDE controllers in a system.
> 	
> 	The problem is that pcibios_fixups table (in arch/i386/pci/fixup.c)
uses
> 	the pci_fixup_ide_trash() quirk for Intel's ICH3 (my case
specifically
> 	8086:248b).  This clears any bogus BAR information set up by the
BIOS.
> 	
> 	In a system which has multiple ICH3's can't use any of the IDE
> 	controllers beside the one on the first ICH3.
> 	
> 	Anyhow, the fix is to make sure pci_fixup_ide_trash resets the BARs
only
> 	for first time being called, so the subsequent IDE controllers will
use
> 	the BIOS BARs.  This is better than "loosing" all these IDE
controllers
> 	in the case their BARs set right.

I do not think this is correct.

The programming interface register tells us if we're in legacy or native 
mode, which is what this fixup is concerned with, AFAICS.

So, the code should base its actions on whether or not the controller is 
in legacy mode, _not_ ordering.

	Jeff




      reply	other threads:[~2004-05-16  4:23 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <200405151813.i4FIDoqt029818@hera.kernel.org>
2004-05-15 18:57 ` Jeff Garzik
2004-05-16  4:20   ` Shai Fultheim [this message]

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