Re: ACPI on Averatec 2370

["Joachim Deguara" <joachim.deguara@amd.com>]

On Wednesday 08 August 2007 02:06:31 Andi Kleen wrote:
> On Tue, Aug 07, 2007 at 06:15:37PM -0400, Cal Peake wrote:
> > On Fri, 3 Aug 2007, Linus Torvalds wrote:
> > > > MSR_K8_ENABLE_C1E lo == 0x04c14015
> > > > MSR_K8_ENABLE_C1E hi == 0x00000000
> > > > lo & ENABLE_C1E_MASK == 0
> > >
> > > And yeah, that claims that C1E is not on, but:
> > > > amd_apic_timer_broken: forcing return value of 1
> >
> > So it seems my initial debugging report was, err, incomplete. I failed to
> > notice that the amd_apic_timer_broken function was getting called twice,
> > once for each core.
> >
> > The second call shows this:
> >
> >   MSR_K8_ENABLE_C1E == 0x14c14015
>
> Ah interesting. Ok finally that all starts making sense.
>
> Not sure why the MSR varies between cores though.

This is a BIOS bug as the BIOS should have programmed the MSR the same for 
both cores.  See section 10.2.4 of the Rev F BKDG [1] (10.2.4.1 talks about 
the SMI case but a newer version of the doc not yet release has similar 
wording about both cores needing to have the bit set for the chipset case).

-Joachim

[1] 
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf