LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To: akpm@linux-foundation.org
Cc: David Brownell <david-b@pacbell.net>,
	Haavard Skinnemoen <hskinnemoen@atmel.com>,
	spi-devel-general@lists.sourceforge.net,
	linux-kernel@vger.kernel.org
Subject: [PATCH] atmel_spi: Fix clock polarity
Date: Thu, 21 Feb 2008 11:11:38 +0900 (JST)	[thread overview]
Message-ID: <20080221.111138.41629131.nemoto@toshiba-tops.co.jp> (raw)

The atmel_spi driver does not initialize clock polarity correctly
(except for at91rm9200 CS0 channel) in some case.

The atmel_spi driver uses gpio-controlled chipselect.  OTOH spi clock
signal is controlled by CSRn.CPOL bit, but this register controls
clock signal correctly only in 'real transfer' duration.  At the time
of cs_activate() call, CSRn.CPOL will be initialized correctly, but
the controller do not know which channel is to be used next, so clock
signal will stay at the inactive state of last transfer.  If clock
polarity of new transfer and last transfer was differ, new transfer
will start with wrong clock signal state.

For example, if you started SPI MODE 2 or 3 transfer after SPI MODE 0
or 1 transfer, the clock signal state at the assertion of chipselect
will be low.  Of course this will violates SPI transfer.

This patch is short term solution for this problem.  It makes all
CSRn.CPOL match for the transfer before activating chipselect.  For
longer term, the best fix might be to let NPCS0 stay selected
permanently in MR and overwrite CSR0 with to the new slave's settings
before asserting CS.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
---
This patch is already in mm tree as atmel_spi-fix-clock-polarity.patch.
I just rewrite description slightly and add my signed-off and acked-by
from Haavard Skinnemoen.

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 293b7ca..85687aa 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -87,6 +87,16 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 	unsigned gpio = (unsigned) spi->controller_data;
 	unsigned active = spi->mode & SPI_CS_HIGH;
 	u32 mr;
+	int i;
+	u32 csr;
+	u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
+
+	/* Make sure clock polarity is correct */
+	for (i = 0; i < spi->master->num_chipselect; i++) {
+		csr = spi_readl(as, CSR0 + 4 * i);
+		if ((csr ^ cpol) & SPI_BIT(CPOL))
+			spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
+	}
 
 	mr = spi_readl(as, MR);
 	mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);

             reply	other threads:[~2008-02-21  2:11 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-02-21  2:11 Atsushi Nemoto [this message]
2008-02-23  8:05 ` Andrew Morton
2008-02-24  0:56   ` Haavard Skinnemoen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20080221.111138.41629131.nemoto@toshiba-tops.co.jp \
    --to=anemo@mba.ocn.ne.jp \
    --cc=akpm@linux-foundation.org \
    --cc=david-b@pacbell.net \
    --cc=hskinnemoen@atmel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=spi-devel-general@lists.sourceforge.net \
    --subject='Re: [PATCH] atmel_spi: Fix clock polarity' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).