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* [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition
@ 2008-10-25  0:21 Alok Kataria
  2008-10-27 11:02 ` Ingo Molnar
  0 siblings, 1 reply; 2+ messages in thread
From: Alok Kataria @ 2008-10-25  0:21 UTC (permalink / raw)
  To: H. Peter Anvin
  Cc: Andi Kleen, Ingo Molnar, LKML, the arch/x86 maintainers, Daniel Hecht

Hi,

These patches define a framework for hypervisor detection and setting of
hypervisor feature bits. We define a X86_FEATURE_TSC_RELIABLE bit which
is a synthetic bit. This is set when running under VMware. This  feature
bit is used to skip TSC checks which can fail on virtualization platform
due to timing differences when running on virtual cpus.

Thanks,
Alok



^ permalink raw reply	[flat|nested] 2+ messages in thread
* Re: [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition
  2008-10-25  0:21 [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition Alok Kataria
@ 2008-10-27 11:02 ` Ingo Molnar
  0 siblings, 0 replies; 2+ messages in thread
From: Ingo Molnar @ 2008-10-27 11:02 UTC (permalink / raw)
  To: Alok Kataria
  Cc: H. Peter Anvin, Andi Kleen, LKML, the arch/x86 maintainers, Daniel Hecht


* Alok Kataria <akataria@vmware.com> wrote:

> Hi,
> 
> These patches define a framework for hypervisor detection and 
> setting of hypervisor feature bits. We define a 
> X86_FEATURE_TSC_RELIABLE bit which is a synthetic bit. This is set 
> when running under VMware. This feature bit is used to skip TSC 
> checks which can fail on virtualization platform due to timing 
> differences when running on virtual cpus.

okay, this looks a lot better structurally - the DMI angle and the 
synthetic CPU flag, and the clocksource smarts are all a clean 
approach. Peter, any objections?

	Ingo

^ permalink raw reply	[flat|nested] 2+ messages in thread
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2008-10-25  0:21 [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition Alok Kataria
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