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From: Ingo Molnar <email@example.com>
To: Micha Nelissen <firstname.lastname@example.org>
Cc: Thomas Gleixner <email@example.com>,
Ingo Molnar <firstname.lastname@example.org>, "H. Peter Anvin" <email@example.com>,
firstname.lastname@example.org, "Venkatesh Pallipadi (Venki)" <email@example.com>,
Jesse Barnes <firstname.lastname@example.org>,
Matthew Wilcox <email@example.com>,
"Eric W. Biederman" <firstname.lastname@example.org>,
Yinghai Lu <email@example.com>,
Suresh Siddha <firstname.lastname@example.org>,
Arjan van de Ven <email@example.com>,
Konrad Rzeszutek Wilk <firstname.lastname@example.org>,
Stefano Stabellini <email@example.com>,
Ben Hutchings <firstname.lastname@example.org>,
Jeremy Fitzhardinge <email@example.com>
Subject: Re: [PATCH] Add support for multiple MSI on x86
Date: Tue, 15 Feb 2011 03:38:47 +0100 [thread overview]
Message-ID: <20110215023847.GF31134@elte.hu> (raw)
* Micha Nelissen <firstname.lastname@example.org> wrote:
> Ingo Molnar wrote:
> >* Micha Nelissen <email@example.com> wrote:
> >>Patch is based on earlier patch from Matthew Wilcox.
> >Hm, there's an awful lot of 'background', 'implementation',
> >'advantages', 'disadvantages', 'testing' description missing.
> Sorry, my bad, wrong assumption that this would be common knowledge.
When it comes to changes done to a kernel tree used by millions of people then
common knowledge and mundane details need to be written down, in painstaking detail.
You cannot really err when it comes to details: i've reviewed over a ten thousand
patches in my life and i've yet to see a single one where the description was too
> PCI devices interrupt the CPU using 'legacy' INTx; or PCI-e devices
> can do a special write, called an MSI (message signaled interrupt).
> The interrupt vector is chosen by the CPU, different devices use
> different vectors so that software can keep the interrupt sources
> separate (instead of using shared INTx "lines").
> Most PCI-e devices support what's called MSI-X, but not all do.
> Especially for FPGA based endpoints it's easier to implement only
> 'regular' MSI support. MSI-X basically involves implementing a
> lookup table that maps interrupt types in the device to interrupt
> vectors for the CPU. 'Regular' MSI (non MSI-X) only supports a
> contiguous block of interrupt vectors: a base vector with a vector
> count (which is a power of 2).
> The x86 code to allocate these interrupt vectors does not handle the
> <> 1 vector count case; it would return that it could only handle 1.
> So either device drivers had 1 MSI, or the device should support
> MSI-X to have multiple interrupts (and handlers) for one device.
> This patch adds the needed code to support multiple MSI per device.
> Advantages: separate interrupt handlers for separate tasks in the
> device. This allows device drivers to be better structured. Easy
> 'diagnostics' due to /proc/interrupts counting number of interrupts
> for separate functionality separately.
> Disadvantages: more complex code due to requirement that it is a
> contiguous block, so needs some effort to look for a free block with
> the requested count.
> Tested: on an Atom platform, with a Xilinx based PCI-e core in FPGA.
> Please review; thanks,
That was a good description, thanks Micha!
next prev parent reply other threads:[~2011-02-15 2:39 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-13 20:25 Micha Nelissen
2011-02-14 12:34 ` Ingo Molnar
2011-02-14 19:47 ` Micha Nelissen
2011-02-15 2:38 ` Ingo Molnar [this message]
2011-02-14 20:55 ` Thomas Gleixner
2011-03-04 18:37 ` Jesse Barnes
2011-06-17 17:12 ` Matthew Wilcox
2011-03-04 18:36 ` Jesse Barnes
2011-03-04 19:53 ` Micha Nelissen
2011-03-08 21:05 ` Thomas Gleixner
[not found] ` <firstname.lastname@example.org>
2011-03-08 21:16 ` Thomas Gleixner
[not found] ` <email@example.com>
2011-03-08 22:13 ` Thomas Gleixner
2011-03-10 2:05 ` Roland Dreier
2011-03-10 15:33 ` Clemens Ladisch
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