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From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Zidan Wang <zidan.wang@freescale.com>
Cc: timur@tabi.org, Xiubo.Lee@gmail.com, lgirdwood@gmail.com,
	broonie@kernel.org, perex@perex.cz, tiwai@suse.de,
	alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org,
	linux-kernel@vger.kernel.org
Subject: Re: [alsa-devel][PATCH 1/3] SoC: fsl_sai: add sai master mode support
Date: Tue, 20 Jan 2015 22:07:03 -0800	[thread overview]
Message-ID: <20150121060702.GB3275@Alpha> (raw)
In-Reply-To: <1421756480-7055-2-git-send-email-zidan.wang@freescale.com>

On Tue, Jan 20, 2015 at 08:21:18PM +0800, Zidan Wang wrote:
> +static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)

> +	if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
> +		regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
> +			FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai->mclk_id));
> +		regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
> +			FSL_SAI_CR2_DIV_MASK, savediv - 1);

Hmm...the case should be a bit more complicated here IMO.

"tx && sai->synchronous[TX]" means the playback in synchronous
mode (TX following RX). What if the recording has been already
activated with an MSEL setting at this point? Then the playback
stream, as a secondary stream, will overwrite MSEL of the first
stream -- Record. Same would happen to the DIV configuration.

> @@ -297,6 +368,24 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
>  	unsigned int channels = params_channels(params);
>  	u32 word_width = snd_pcm_format_width(params_format(params));
>  	u32 val_cr4 = 0, val_cr5 = 0;
> +	int ret;
> +
> +	if (!sai->is_slave_mode) {
> +		ret = fsl_sai_set_bclk(cpu_dai, tx,
> +			2 * word_width * params_rate(params));
> +		if (ret)
> +			return ret;
> +
> +		/* Do not enable the clock if it is already enabled */

It actually doesn't matter to enable the clock again since it
purely increaes its count. But we do need a protection for MSEL
overwritten issue resulted from the fsl_sai_set_bclk() call.

> @@ -133,10 +135,13 @@ struct fsl_sai {
>  	struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
>  
>  	bool is_lsb_first;
> +	bool is_slave_mode;
>  	bool is_dsp_mode;
>  	bool sai_on_imx;
>  	bool synchronous[2];
>  
> +	unsigned int mclk_id;
> +	unsigned int mclk_streams;

Besides, I doubt that only one property of mclk_id can content
Asynchronous Mode -- TX and RX can fetch their clocks from
different MCLK sources.

Nicolin

  reply	other threads:[~2015-01-21  6:07 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-20 12:21 [alsa-devel][PATCH 0/3] Add master mode, tmd and right-j " Zidan Wang
2015-01-20 12:21 ` [alsa-devel][PATCH 1/3] SoC: fsl_sai: add sai master " Zidan Wang
2015-01-21  6:07   ` Nicolin Chen [this message]
2015-01-21  9:25     ` Zidan Wang
2015-01-21 17:36       ` Nicolin Chen
2015-01-20 12:21 ` [alsa-devel][PATCH 2/3] ASoC: fsl_sai: Add support for tdm slots operation Zidan Wang
2015-01-21 18:08   ` Nicolin Chen
2015-01-22  4:55     ` Zidan Wang
2015-01-22  5:44       ` Nicolin Chen
2015-01-22  6:20         ` Zidan Wang
2015-01-22 23:50           ` Nicolin Chen
2015-01-23  2:55             ` Zidan Wang
2015-01-23  8:27               ` Nicolin Chen
2015-01-20 12:21 ` [alsa-devel][PATCH 3/3] ASoC: fsl_sai: Add support for Right-J mode Zidan Wang
2015-01-21 18:53   ` Nicolin Chen
2015-01-22  5:13     ` Zidan Wang
2015-01-22  5:46       ` Nicolin Chen
2015-01-21  1:15 ` [alsa-devel] [PATCH 0/3] Add master mode, tmd and right-j mode support Fabio Estevam
2015-01-21  6:29   ` Nicolin Chen

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